<def f='src/src/sys/dev/pci/vioscsireg.h' l='64' ll='71'/>
<size>108</size>
<doc f='src/src/sys/dev/pci/vioscsireg.h' l='63'>/* Response header structure */</doc>
<mbr r='virtio_scsi_res_hdr::sense_len' o='0' t='__uint32_t'/>
<mbr r='virtio_scsi_res_hdr::residual' o='32' t='__uint32_t'/>
<mbr r='virtio_scsi_res_hdr::status_qualifier' o='64' t='__uint16_t'/>
<mbr r='virtio_scsi_res_hdr::status' o='80' t='__uint8_t'/>
<mbr r='virtio_scsi_res_hdr::response' o='88' t='__uint8_t'/>
<mbr r='virtio_scsi_res_hdr::sense' o='96' t='__uint8_t [96]'/>
