<dec f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/include/subdev/clock.h' l='61' type='u8'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/device/nouveau_engine_device_ctrl.c' l='99' u='r' c='nouveau_control_mthd_pstate_attr'/>
<offset>1344</offset>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='159' u='r' c='nouveau_cstate_new'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='233' u='r' c='nouveau_pstate_info'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='234' u='r' c='nouveau_pstate_info'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='304' u='w' c='nouveau_pstate_new'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='323' u='r' c='nouveau_pstate_new'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='331' u='r' c='nouveau_pstate_new'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='359' u='r' c='nouveau_clock_ustate_update'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='364' u='r' c='nouveau_clock_ustate_update'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_base.c' l='424' u='w' c='_nouveau_clock_init'/>
