<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='1069' type='u8'/>
<offset>328</offset>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='1069'>/* AKA RPe. Pre-determined balanced frequency */</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c' l='1148' u='r' c='gen6_pm_rps_work'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c' l='1149' u='r' c='gen6_pm_rps_work'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c' l='1151' u='r' c='gen6_pm_rps_work'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_irq.c' l='1152' u='r' c='gen6_pm_rps_work'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='2992' u='r' c='gen6_set_rps_thresholds'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='2997' u='r' c='gen6_set_rps_thresholds'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='3423' u='w' c='gen6_enable_rps'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='3761' u='w' c='valleyview_enable_rps'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='3763' u='r' c='valleyview_enable_rps'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='3764' u='r' c='valleyview_enable_rps'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='3779' u='r' c='valleyview_enable_rps'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='3780' u='r' c='valleyview_enable_rps'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='3782' u='r' c='valleyview_enable_rps'/>
