diff -ruN pciutils-2.2.6/ChangeLog pciutils-2.2.7/ChangeLog
--- pciutils-2.2.6/ChangeLog	2007-06-20 20:47:40.000000000 +0200
+++ pciutils-2.2.7/ChangeLog	2007-10-05 14:21:57.000000000 +0200
@@ -1,3 +1,55 @@
+2007-10-05  Martin Mares <mj@ucw.cz>
+
+	* Released as 2.2.7.
+
+	* lspci.c (show_caps, show_ext_caps): Detect and report loops in
+	capability lists.
+
+	* lspci.c, lib/header.h: Finished decoding of the PCI Express
+	capability. The extended capabilities remain undecoded for now,
+	but at least the list of them has been updated to reflect the
+	current PCI Express 2.0 spec.
+
+	* lspci.c, lib/header.h: Decode new bits of traditional registers
+	as defined by PCIE / PCI-X. This includes discard timers in the bridge
+	control register and INTx enable/status in device control/status
+	registers.
+
+	* lib/fbsd-device.c: Support domains on new FreeBSD's. Contributed
+	by Marius Strobl.
+
+2007-09-12  Hasso Tepper <hasso@estpak.ee>
+
+	* Extended the fbsd-device backend to run on Dragonfly BSD.
+
+	* lspci.c: alloca() is declared in <stdlib.h> on BSD's, not <alloca.h>.
+
+2007-09-03  Martin Mares <mj@ucw.cz>
+
+	* Resurrected the Windows port, including cross-compilation by MinGW.
+	Patch by Samuel Bronson <naesten@gmail.com>.
+
+2007-08-31  Martin Mares <mj@ucw.cz>
+
+	* Makefile, lib/Makefile: `ar' and `ranlib' can be overriden to allow
+	cross-compilation.
+
+2007-08-27  Martin Mares  <mj@ucw.cz>
+
+	* lib/names.c (pci_open): When calling gzopen(), use "rb" file mode
+	instead of "r". This is needed on DOS systems, where this function
+	somewhat illogically uses the binary flag for the compressed file
+	instead of the decompressed stream inside, where binariness really
+	matters.
+
+2007-08-14  Martin Mares  <mj@ucw.cz>
+
+	* lspci.c (show_ht): Added decoding of Hypertransport MSI mapping capability,
+	based on a patch by Jason Gunthorpe.
+
+	* tests/cap-MSI-mapping: Added a test case. I plan to add test cases
+	(which are dumps of config space) for all new features.
+
 2007-06-20  Martin Mares  <mj@ucw.cz>
 
 	* Released as 2.2.6.
diff -ruN pciutils-2.2.6/Makefile pciutils-2.2.7/Makefile
--- pciutils-2.2.6/Makefile	2007-06-20 20:47:02.000000000 +0200
+++ pciutils-2.2.7/Makefile	2007-10-05 14:22:06.000000000 +0200
@@ -4,8 +4,8 @@
 OPT=-O2
 CFLAGS=$(OPT) -Wall -W -Wno-parentheses -Wstrict-prototypes -Wmissing-prototypes
 
-VERSION=2.2.6
-DATE=2007-06-20
+VERSION=2.2.7
+DATE=2007-10-05
 
 PREFIX=/usr/local
 SBINDIR=$(PREFIX)/sbin
@@ -17,6 +17,8 @@
 PKGCFDIR=$(LIBDIR)/pkgconfig
 INSTALL=install
 DIRINSTALL=install -d
+AR=ar
+RANLIB=ranlib
 PCILIB=lib/libpci.a
 PCILIBPC=lib/libpci.pc
 PCIINC=lib/config.h lib/header.h lib/pci.h lib/types.h lib/sysdep.h
diff -ruN pciutils-2.2.6/README pciutils-2.2.7/README
--- pciutils-2.2.6/README	2007-06-20 20:48:06.000000000 +0200
+++ pciutils-2.2.7/README	2007-10-05 14:22:33.000000000 +0200
@@ -1,4 +1,4 @@
-This package contains the PCI Utilities, version 2.2.6.
+This package contains the PCI Utilities, version 2.2.7.
 
 Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
 
diff -ruN pciutils-2.2.6/README.Windows pciutils-2.2.7/README.Windows
--- pciutils-2.2.6/README.Windows	2006-07-30 12:36:19.000000000 +0200
+++ pciutils-2.2.7/README.Windows	2007-09-03 10:44:15.000000000 +0200
@@ -1,8 +1,11 @@
 Since 2.1.99-test5, pciutils should also be compilable on Windows. Thanks
 to Alexander Stock for contributing the port.
 
-To build this port, you need to install WinIO.dll first. You can get it
+Updated after version 2.2.6 to compile again, and with MinGW, even (only?)
+cross-compiling. (Hopefully it works with MSVC too.)
+
+To use this port, you need to install WinIO.dll first. You can get it
 from http://www.internals.com/.
 
-However, you need to use win32/config.h instead of the automatically
-generated lib/config.h as lib/configure does not run on Windows.
+However, you need to use win32/config.{h,mk} instead of the automatically
+generated lib/config.{h,mk} as lib/configure does not run on Windows.
diff -ruN pciutils-2.2.6/lib/Makefile pciutils-2.2.7/lib/Makefile
--- pciutils-2.2.6/lib/Makefile	2007-06-20 20:43:16.000000000 +0200
+++ pciutils-2.2.7/lib/Makefile	2007-08-31 10:56:20.000000000 +0200
@@ -54,8 +54,8 @@
 
 $(PCILIB): $(OBJS)
 	rm -f $@
-	ar rcs $@ $^
-	ranlib $@
+	$(AR) rcs $@ $^
+	$(RANLIB) $@
 
 $(PCILIBPC): $(PCILIBPC).in
 	sed <$< >$@ -e 's,@PREFIX@,$(PREFIX),' \
diff -ruN pciutils-2.2.6/lib/configure pciutils-2.2.7/lib/configure
--- pciutils-2.2.6/lib/configure	2007-06-20 20:43:16.000000000 +0200
+++ pciutils-2.2.7/lib/configure	2007-09-12 21:24:40.000000000 +0200
@@ -22,7 +22,7 @@
 else
 	cpu=`uname -m | sed 's/^i.86$/i386/;s/^sun4u$/sparc64/;s/^i86pc$/i386/'`
 fi
-if [ "$sys" = "GNU/kFreeBSD" ]
+if [ "$sys" = "GNU/kFreeBSD" -o "$sys" = "DragonFly" ]
 then
 	sys=freebsd
 fi
diff -ruN pciutils-2.2.6/lib/fbsd-device.c pciutils-2.2.7/lib/fbsd-device.c
--- pciutils-2.2.6/lib/fbsd-device.c	2006-09-09 12:52:42.000000000 +0200
+++ pciutils-2.2.7/lib/fbsd-device.c	2007-10-05 14:20:56.000000000 +0200
@@ -7,7 +7,9 @@
  *	Can be freely distributed and used under the terms of the GNU GPL.
  */
 
+#include <errno.h>
 #include <fcntl.h>
+#include <stdio.h>
 #include <string.h>
 #include <unistd.h>
 #include <osreldate.h>
@@ -19,13 +21,8 @@
 #  endif
 #endif
 
-#if __FreeBSD_version < 500000
+#if __FreeBSD_version < 430000 && !defined(__DragonFly__)
 #  include <pci/pcivar.h>
-#else
-#  include <dev/pci/pcivar.h>
-#endif
-
-#if __FreeBSD_version < 430000
 #  include <pci/pci_ioctl.h>
 #else
 #  include <sys/pciio.h>
@@ -84,6 +81,9 @@
   if (pos >= 256)
     return 0;
 
+#if __FreeBSD_version >= 700053
+  pi.pi_sel.pc_domain = d->domain;
+#endif
   pi.pi_sel.pc_bus = d->bus;
   pi.pi_sel.pc_dev = d->dev;
   pi.pi_sel.pc_func = d->func;
@@ -92,7 +92,13 @@
   pi.pi_width = len;
 
   if (ioctl(d->access->fd, PCIOCREAD, &pi) < 0)
-    d->access->error("fbsd_read: ioctl(PCIOCREAD) failed");
+    {
+      if (errno == ENODEV)
+        {
+          return 0;
+        }
+      d->access->error("fbsd_read: ioctl(PCIOCREAD) failed: %s", strerror(errno));
+    }
 
   switch (len)
     {
@@ -100,10 +106,10 @@
       buf[0] = (u8) pi.pi_data;
       break;
     case 2:
-      ((u16 *) buf)[0] = (u16) pi.pi_data;
+      ((u16 *) buf)[0] = cpu_to_le16((u16) pi.pi_data);
       break;
     case 4:
-      ((u32 *) buf)[0] = (u32) pi.pi_data;
+      ((u32 *) buf)[0] = cpu_to_le32((u32) pi.pi_data);
       break;
     }
   return 1;
@@ -122,6 +128,9 @@
   if (pos >= 256)
     return 0;
 
+#if __FreeBSD_version >= 700053
+  pi.pi_sel.pc_domain = d->domain;
+#endif
   pi.pi_sel.pc_bus = d->bus;
   pi.pi_sel.pc_dev = d->dev;
   pi.pi_sel.pc_func = d->func;
@@ -135,16 +144,20 @@
       pi.pi_data = buf[0];
       break;
     case 2:
-      pi.pi_data = ((u16 *) buf)[0];
+      pi.pi_data = le16_to_cpu(((u16 *) buf)[0]);
       break;
     case 4:
-      pi.pi_data = ((u32 *) buf)[0];
+      pi.pi_data = le32_to_cpu(((u32 *) buf)[0]);
       break;
     }
 
   if (ioctl(d->access->fd, PCIOCWRITE, &pi) < 0)
     {
-      d->access->error("fbsd_write: ioctl(PCIOCWRITE) failed");
+      if (errno == ENODEV)
+        {
+          return 0;
+        }
+      d->access->error("fbsd_write: ioctl(PCIOCWRITE) failed: %s", strerror(errno));
     }
 
   return 1;
diff -ruN pciutils-2.2.6/lib/header.h pciutils-2.2.7/lib/header.h
--- pciutils-2.2.6/lib/header.h	2007-02-14 20:37:46.000000000 +0100
+++ pciutils-2.2.7/lib/header.h	2007-10-05 14:04:18.000000000 +0200
@@ -1,7 +1,7 @@
 /*
  *	The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
  *
- *	Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
+ *	Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
  *
  *	Can be freely distributed and used under the terms of the GNU GPL.
  */
@@ -23,8 +23,10 @@
 #define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
 #define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
 #define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
+#define  PCI_COMMAND_DISABLE_INTx	0x400	/* PCIE: Disable INTx interrupts */
 
 #define PCI_STATUS		0x06	/* 16 bits */
+#define  PCI_STATUS_INTx	0x08	/* PCIE: INTx interrupt pending */
 #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
 #define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
 #define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
@@ -136,6 +138,10 @@
 #define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
 #define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
 #define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
+#define  PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100		/* PCI-X? */
+#define  PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200		/* PCI-X? */
+#define  PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400	/* PCI-X? */
+#define  PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800	/* PCI-X? */
 
 /* Header type 2 (CardBus bridges) */
 /* 0x14-0x15 reserved */
@@ -202,6 +208,13 @@
 #define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel */
 #define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
 #define PCI_EXT_CAP_ID_PB	0x04	/* Power Budgeting */
+#define PCI_EXT_CAP_ID_RCLINK	0x05	/* Root Complex Link Declaration */
+#define PCI_EXT_CAP_ID_RCILINK	0x06	/* Root Complex Internal Link Declaration */
+#define PCI_EXT_CAP_ID_RCECOLL	0x07	/* Root Complex Event Collector */
+#define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function Virtual Channel */
+#define PCI_EXT_CAP_ID_RBCB	0x0a	/* Root Bridge Control Block */
+#define PCI_EXT_CAP_ID_VNDR	0x0b	/* Vendor specific */
+#define PCI_EXT_CAP_ID_ACS	0x0d	/* Access Controls */
 
 /* Power Management Registers */
 
@@ -692,6 +705,8 @@
 #define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
 #define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
 #define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIE Bridge */
+#define  PCI_EXP_TYPE_ROOT_INT_EP 0x9	/* Root Complex Integrated Endpoint */
+#define  PCI_EXP_TYPE_ROOT_EC 0xa	/* Root Complex Event Collector */
 #define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
 #define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
 #define PCI_EXP_DEVCAP		0x4	/* Device capabilities */
@@ -703,8 +718,10 @@
 #define  PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
 #define  PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Indicator Present */
 #define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
+#define  PCI_EXP_DEVCAP_RBE	0x8000	/* Role-Based Error Reporting */
 #define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
 #define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
+#define  PCI_EXP_DEVCAP_FLRESET	0x10000000 /* Function-Level Reset */
 #define PCI_EXP_DEVCTL		0x8	/* Device Control */
 #define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
 #define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
@@ -717,6 +734,8 @@
 #define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
 #define  PCI_EXP_DEVCTL_NOSNOOP	0x0800	/* Enable No Snoop */
 #define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
+#define  PCI_EXP_DEVCTL_BCRE	0x8000	/* Bridge Configuration Retry Enable */
+#define  PCI_EXP_DEVCTL_FLRESET	0x8000	/* Function-Level Reset [bit shared with BCRE] */
 #define PCI_EXP_DEVSTA		0xa	/* Device Status */
 #define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
 #define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
@@ -730,6 +749,10 @@
 #define  PCI_EXP_LNKCAP_ASPM	0x00c00	/* Active State Power Management */
 #define  PCI_EXP_LNKCAP_L0S	0x07000	/* L0s Acceptable Latency */
 #define  PCI_EXP_LNKCAP_L1	0x38000	/* L1 Acceptable Latency */
+#define  PCI_EXP_LNKCAP_CLOCKPM	0x40000	/* Clock Power Management */
+#define  PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */
+#define  PCI_EXP_LNKCAP_DLLA	0x100000 /* Data Link Layer Active Reporting */
+#define  PCI_EXP_LNKCAP_LBNC	0x200000 /* Link Bandwidth Notification Capability */
 #define  PCI_EXP_LNKCAP_PORT	0xff000000 /* Port Number */
 #define PCI_EXP_LNKCTL		0x10	/* Link Control */
 #define  PCI_EXP_LNKCTL_ASPM	0x0003	/* ASPM Control */
@@ -738,12 +761,19 @@
 #define  PCI_EXP_LNKCTL_RETRAIN	0x0020	/* Retrain Link */
 #define  PCI_EXP_LNKCTL_CLOCK	0x0040	/* Common Clock Configuration */
 #define  PCI_EXP_LNKCTL_XSYNCH	0x0080	/* Extended Synch */
+#define  PCI_EXP_LNKCTL_CLOCKPM	0x0100	/* Clock Power Management */
+#define  PCI_EXP_LNKCTL_HWAUTWD	0x0200	/* Hardware Autonomous Width Disable */
+#define  PCI_EXP_LNKCTL_BWMIE	0x0400	/* Bandwidth Mgmt Interrupt Enable */
+#define  PCI_EXP_LNKCTL_AUTBWIE	0x0800	/* Autonomous Bandwidth Mgmt Interrupt Enable */
 #define PCI_EXP_LNKSTA		0x12	/* Link Status */
 #define  PCI_EXP_LNKSTA_SPEED	0x000f	/* Negotiated Link Speed */
 #define  PCI_EXP_LNKSTA_WIDTH	0x03f0	/* Negotiated Link Width */
-#define  PCI_EXP_LNKSTA_TR_ERR	0x0400	/* Training Error */
+#define  PCI_EXP_LNKSTA_TR_ERR	0x0400	/* Training Error (obsolete) */
 #define  PCI_EXP_LNKSTA_TRAIN	0x0800	/* Link Training */
 #define  PCI_EXP_LNKSTA_SL_CLK	0x1000	/* Slot Clock Configuration */
+#define  PCI_EXP_LNKSTA_DL_ACT	0x2000	/* Data Link Layer in DL_Active State */
+#define  PCI_EXP_LNKSTA_BWMGMT	0x4000	/* Bandwidth Mgmt Status */
+#define  PCI_EXP_LNKSTA_AUTBW	0x8000	/* Autonomous Bandwidth Mgmt Status */
 #define PCI_EXP_SLTCAP		0x14	/* Slot Capabilities */
 #define  PCI_EXP_SLTCAP_ATNB	0x0001	/* Attention Button Present */
 #define  PCI_EXP_SLTCAP_PWRC	0x0002	/* Power Controller Present */
@@ -754,6 +784,8 @@
 #define  PCI_EXP_SLTCAP_HPC	0x0040	/* Hot-Plug Capable */
 #define  PCI_EXP_SLTCAP_PWR_VAL	0x00007f80 /* Slot Power Limit Value */
 #define  PCI_EXP_SLTCAP_PWR_SCL	0x00018000 /* Slot Power Limit Scale */
+#define  PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */
+#define  PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */
 #define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
 #define PCI_EXP_SLTCTL		0x18	/* Slot Control */
 #define  PCI_EXP_SLTCTL_ATNB	0x0001	/* Attention Button Pressed Enable */
@@ -762,16 +794,33 @@
 #define  PCI_EXP_SLTCTL_PRSD	0x0008	/* Presence Detect Changed Enable */
 #define  PCI_EXP_SLTCTL_CMDC	0x0010	/* Command Completed Interrupt Enable */
 #define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */
-#define  PCI_EXP_SLTCTL_ATNI	0x00C0	/* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_ATNI	0x00c0	/* Attention Indicator Control */
 #define  PCI_EXP_SLTCTL_PWRI	0x0300	/* Power Indicator Control */
 #define  PCI_EXP_SLTCTL_PWRC	0x0400	/* Power Controller Control */
+#define  PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */
+#define  PCI_EXP_SLTCTL_LLCHG	0x1000	/* Data Link Layer State Changed Enable */
 #define PCI_EXP_SLTSTA		0x1a	/* Slot Status */
+#define  PCI_EXP_SLTSTA_ATNB	0x0001	/* Attention Button Pressed */
+#define  PCI_EXP_SLTSTA_PWRF	0x0002	/* Power Fault Detected */
+#define  PCI_EXP_SLTSTA_MRLS	0x0004	/* MRL Sensor Changed */
+#define  PCI_EXP_SLTSTA_PRSD	0x0008	/* Presence Detect Changed */
+#define  PCI_EXP_SLTSTA_CMDC	0x0010	/* Command Completed */
+#define  PCI_EXP_SLTSTA_MRL_ST	0x0020	/* MRL Sensor State */
+#define  PCI_EXP_SLTSTA_PRES	0x0040	/* Presence Detect State */
+#define  PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */
+#define  PCI_EXP_SLTSTA_LLCHG	0x0100	/* Data Link Layer State Changed */
 #define PCI_EXP_RTCTL		0x1c	/* Root Control */
-#define  PCI_EXP_RTCTL_SECEE	0x1	/* System Error on Correctable Error */
-#define  PCI_EXP_RTCTL_SENFEE	0x1	/* System Error on Non-Fatal Error */
-#define  PCI_EXP_RTCTL_SEFEE	0x1	/* System Error on Fatal Error */
-#define  PCI_EXP_RTCTL_PMEIE	0x1	/* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_SECEE	0x0001	/* System Error on Correctable Error */
+#define  PCI_EXP_RTCTL_SENFEE	0x0002	/* System Error on Non-Fatal Error */
+#define  PCI_EXP_RTCTL_SEFEE	0x0004	/* System Error on Fatal Error */
+#define  PCI_EXP_RTCTL_PMEIE	0x0008	/* PME Interrupt Enable */
+#define  PCI_EXP_RTCTL_CRSVIS	0x0010	/* Configuration Request Retry Status Visible to SW */
+#define PCI_EXP_RTCAP		0x1e	/* Root Capabilities */
+#define  PCI_EXP_RTCAP_CRSVIS	0x0010	/* Configuration Request Retry Status Visible to SW */
 #define PCI_EXP_RTSTA		0x20	/* Root Status */
+#define  PCI_EXP_RTSTA_PME_REQID   0x0000ffff /* PME Requester ID */
+#define  PCI_EXP_RTSTA_PME_STATUS  0x00010000 /* PME Status */
+#define  PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
 
 /* MSI-X */
 #define  PCI_MSIX_ENABLE	0x8000
diff -ruN pciutils-2.2.6/lib/i386-io-windows.h pciutils-2.2.7/lib/i386-io-windows.h
--- pciutils-2.2.6/lib/i386-io-windows.h	2006-07-30 13:21:36.000000000 +0200
+++ pciutils-2.2.7/lib/i386-io-windows.h	2007-09-03 10:45:22.000000000 +0200
@@ -8,9 +8,19 @@
  */
 
 #include <io.h>
-#include <conio.h>
 #include <windows.h>
 
+#ifndef __GNUC__
+#include <conio.h>
+#else
+int _outp(unsigned short port, int databyte);
+unsigned short _outpw(unsigned short port, unsigned short dataword);
+unsigned long _outpd(unsigned short port, unsigned long dataword);
+int _inp(unsigned short port);
+unsigned short _inpw(unsigned short port);
+unsigned long _inpd(unsigned short port);
+#endif
+
 #define outb(x,y) _outp(y,x)
 #define outw(x,y) _outpw(y,x)
 #define outl(x,y) _outpd(y,x)
@@ -26,8 +36,6 @@
   MYPROC InitializeWinIo;
   HMODULE lib;
 
-  intel_iopl_set = 0;
-
   lib = LoadLibrary("WinIo.dll");
   if (!lib)
     {
diff -ruN pciutils-2.2.6/lib/names.c pciutils-2.2.7/lib/names.c
--- pciutils-2.2.6/lib/names.c	2007-02-06 13:00:10.000000000 +0100
+++ pciutils-2.2.7/lib/names.c	2007-08-27 18:10:22.000000000 +0200
@@ -1,7 +1,7 @@
 /*
  *	The PCI Library -- ID to Name Translation
  *
- *	Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
+ *	Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
  *
  *	Can be freely distributed and used under the terms of the GNU GPL.
  */
@@ -26,7 +26,7 @@
   size_t len;
   char *new_name;
 
-  result = gzopen(a->id_file_name, "r");
+  result = gzopen(a->id_file_name, "rb");
   if (result)
     return result;
   len = strlen(a->id_file_name);
@@ -36,7 +36,7 @@
   memcpy(new_name, a->id_file_name, len - 3);
   new_name[len - 3] = 0;
   pci_set_name_list_path(a, new_name, 1);
-  return gzopen(a->id_file_name, "r");
+  return gzopen(a->id_file_name, "rb");
 }
 
 #define pci_close(f)		gzclose(f)
diff -ruN pciutils-2.2.6/lib/types.h pciutils-2.2.7/lib/types.h
--- pciutils-2.2.6/lib/types.h	2007-02-06 12:54:35.000000000 +0100
+++ pciutils-2.2.7/lib/types.h	2007-09-03 10:44:15.000000000 +0200
@@ -11,9 +11,10 @@
 #ifndef PCI_HAVE_Uxx_TYPES
 
 #ifdef PCI_OS_WINDOWS
-typedef unsigned __int8 u8;
-typedef unsigned __int16 u16;
-typedef unsigned __int32 u32;
+#include <windef.h>
+typedef BYTE u8;
+typedef WORD u16;
+typedef DWORD u32;
 #elif defined(PCI_HAVE_STDINT_H)
 #include <stdint.h>
 typedef uint8_t u8;
diff -ruN pciutils-2.2.6/lspci.c pciutils-2.2.7/lspci.c
--- pciutils-2.2.6/lspci.c	2007-03-30 11:56:35.000000000 +0200
+++ pciutils-2.2.7/lspci.c	2007-10-05 14:14:36.000000000 +0200
@@ -58,8 +58,9 @@
  *  This increases our memory footprint, but only slightly since we don't
  *  use alloca() much.
  */
-
-#ifdef __GNUC__
+#if defined (__FreeBSD__) || defined (__NetBSD__) || defined (__OpenBSD__) || defined (__DragonFly__)
+/* alloca() is defined in stdlib.h */
+#elif defined(__GNUC__) && !defined(PCI_OS_WINDOWS)
 #include <alloca.h>
 #else
 #undef alloca
@@ -941,7 +942,18 @@
       printf("HyperTransport: Address Mapping\n");
       break;
     case PCI_HT_CMD_TYP_MSIM:
-      printf("HyperTransport: MSI Mapping\n");
+      printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
+	     FLAG(cmd, PCI_HT_MSIM_CMD_EN),
+	     FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
+      if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
+	{
+	  u32 offl, offh;
+	  if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
+	    break;
+	  offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
+	  offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
+	  printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
+	}
       break;
     case PCI_HT_CMD_TYP_DR:
       printf("HyperTransport: DirectRoute\n");
@@ -1077,38 +1089,56 @@
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
-  printf("\t\tDevice: Supported: MaxPayload %d bytes, PhantFunc %d, ExtTag%c\n",
+  printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d, Latency L0s %s, L1 %s\n",
 	128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
 	(1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1,
-	FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
-  printf("\t\tDevice: Latency L0s %s, L1 %s\n",
 	latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 	latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
+  printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
-    printf("\t\tDevice: AtnBtn%c AtnInd%c PwrInd%c\n",
+    printf(" AttnBtn%c AttnInd%c PwrInd%c",
 	FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 	FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
+  printf(" RBE%c FLReset%c",
+	FLAG(t, PCI_EXP_DEVCAP_RBE),
+	FLAG(t, PCI_EXP_DEVCAP_FLRESET));
   if (type == PCI_EXP_TYPE_UPSTREAM)
-    printf("\t\tDevice: SlotPowerLimit %f\n",
+    printf("SlotPowerLimit %fW",
 	power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
 		    (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
+  printf("\n");
 
   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
-  printf("\t\tDevice: Errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
+  printf("\t\tDevCtl:\tReport errors: Correctable%c Non-Fatal%c Fatal%c Unsupported%c\n",
 	FLAG(w, PCI_EXP_DEVCTL_CERE),
 	FLAG(w, PCI_EXP_DEVCTL_NFERE),
 	FLAG(w, PCI_EXP_DEVCTL_FERE),
 	FLAG(w, PCI_EXP_DEVCTL_URRE));
-  printf("\t\tDevice: RlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c\n",
+  printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
 	FLAG(w, PCI_EXP_DEVCTL_RELAXED),
 	FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
 	FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 	FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 	FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
-  printf("\t\tDevice: MaxPayload %d bytes, MaxReadReq %d bytes\n",
+  if (type == PCI_EXP_TYPE_PCI_BRIDGE || type == PCI_EXP_TYPE_PCIE_BRIDGE)
+    printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
+  if (type == PCI_EXP_TYPE_ENDPOINT && (t & PCI_EXP_DEVCAP_FLRESET))
+    printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
+  printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 	128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
 	128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
+
+  w = get_conf_word(d, where + PCI_EXP_DEVSTA);
+  printf("\t\tDevSta:\tCorrErr%c UncorrErr%c FatalErr%c UnsuppReq%c AuxPwr%c TransPend%c\n",
+	FLAG(w, PCI_EXP_DEVSTA_CED),
+	FLAG(w, PCI_EXP_DEVSTA_NFED),
+	FLAG(w, PCI_EXP_DEVSTA_FED),
+	FLAG(w, PCI_EXP_DEVSTA_URD),
+	FLAG(w, PCI_EXP_DEVSTA_AUXPD),
+	FLAG(w, PCI_EXP_DEVSTA_TRPND));
+
+  /* FIXME: Second set of control/status registers is not supported yet. */
 }
 
 static char *link_speed(int speed)
@@ -1116,7 +1146,9 @@
   switch (speed)
     {
       case 1:
-	return "2.5Gb/s";
+	return "2.5GT/s";
+      case 2:
+	return "5GT/s";
       default:
 	return "unknown";
     }
@@ -1147,25 +1179,43 @@
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
-  printf("\t\tLink: Supported Speed %s, Width x%d, ASPM %s, Port %d\n",
+  printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s, Latency L0 %s, L1 %s\n",
+	t >> 24,
 	link_speed(t & PCI_EXP_LNKCAP_SPEED), (t & PCI_EXP_LNKCAP_WIDTH) >> 4,
 	aspm_support((t & PCI_EXP_LNKCAP_ASPM) >> 10),
-	t >> 24);
-  printf("\t\tLink: Latency L0s %s, L1 %s\n",
 	latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12),
 	latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
+  printf("\t\t\tClockPM%c Suprise%c LLActRep%c BwNot%c\n",
+	FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
+	FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
+	FLAG(t, PCI_EXP_LNKCAP_DLLA),
+	FLAG(t, PCI_EXP_LNKCAP_LBNC));
+
   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
-  printf("\t\tLink: ASPM %s", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
+  printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
       (type == PCI_EXP_TYPE_LEG_END))
     printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
-  if (w & PCI_EXP_LNKCTL_DISABLE)
-    printf(" Disabled");
-  printf(" CommClk%c ExtSynch%c\n", FLAG(w, PCI_EXP_LNKCTL_CLOCK),
-	FLAG(w, PCI_EXP_LNKCTL_XSYNCH));
+  printf(" Disabled%c Retrain%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+	FLAG(w, PCI_EXP_LNKCTL_DISABLE),
+	FLAG(w, PCI_EXP_LNKCTL_RETRAIN),
+	FLAG(w, PCI_EXP_LNKCTL_CLOCK),
+	FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
+	FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
+	FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
+	FLAG(w, PCI_EXP_LNKCTL_BWMIE),
+	FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
+
   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
-  printf("\t\tLink: Speed %s, Width x%d\n",
-	link_speed(w & PCI_EXP_LNKSTA_SPEED), (w & PCI_EXP_LNKSTA_WIDTH) >> 4);
+  printf("\t\tLnkSta:\tSpeed %s, Width x%d, TrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
+	link_speed(w & PCI_EXP_LNKSTA_SPEED),
+	(w & PCI_EXP_LNKSTA_WIDTH) >> 4,
+	FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
+	FLAG(w, PCI_EXP_LNKSTA_TRAIN),
+	FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
+	FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
+	FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
+	FLAG(w, PCI_EXP_LNKSTA_AUTBW));
 }
 
 static const char *indicator(int code)
@@ -1180,7 +1230,7 @@
   u16 w;
 
   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
-  printf("\t\tSlot: AtnBtn%c PwrCtrl%c MRL%c AtnInd%c PwrInd%c HotPlug%c Surpise%c\n",
+  printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surpise%c\n",
 	FLAG(t, PCI_EXP_SLTCAP_ATNB),
 	FLAG(t, PCI_EXP_SLTCAP_PWRC),
 	FLAG(t, PCI_EXP_SLTCAP_MRL),
@@ -1188,31 +1238,60 @@
 	FLAG(t, PCI_EXP_SLTCAP_PWRI),
 	FLAG(t, PCI_EXP_SLTCAP_HPC),
 	FLAG(t, PCI_EXP_SLTCAP_HPS));
-  printf("\t\tSlot: Number %d, PowerLimit %f\n", t >> 19,
-		power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7,
-			(t & PCI_EXP_SLTCAP_PWR_SCL) >> 15));
+  printf("\t\t\tSlot #%3x, PowerLimit %f; Interlock%c NoCompl%c\n",
+	t >> 19,
+	power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
+	FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
+	FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
+
   w = get_conf_word(d, where + PCI_EXP_SLTCTL);
-  printf("\t\tSlot: Enabled AtnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c\n",
+  printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
 	FLAG(w, PCI_EXP_SLTCTL_ATNB),
 	FLAG(w, PCI_EXP_SLTCTL_PWRF),
 	FLAG(w, PCI_EXP_SLTCTL_MRLS),
 	FLAG(w, PCI_EXP_SLTCTL_PRSD),
 	FLAG(w, PCI_EXP_SLTCTL_CMDC),
-	FLAG(w, PCI_EXP_SLTCTL_HPIE));
-  printf("\t\tSlot: AttnInd %s, PwrInd %s, Power%c\n",
+	FLAG(w, PCI_EXP_SLTCTL_HPIE),
+	FLAG(w, PCI_EXP_SLTCTL_LLCHG));
+  printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
 	indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
 	indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
-	FLAG(w, w & PCI_EXP_SLTCTL_PWRC));
+	FLAG(w, PCI_EXP_SLTCTL_PWRC),
+	FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
+
+  w = get_conf_word(d, where + PCI_EXP_SLTSTA);
+  printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
+	FLAG(w, PCI_EXP_SLTSTA_ATNB),
+	FLAG(w, PCI_EXP_SLTSTA_PWRF),
+	FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
+	FLAG(w, PCI_EXP_SLTSTA_CMDC),
+	FLAG(w, PCI_EXP_SLTSTA_PRES),
+	FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
+  printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
+	FLAG(w, PCI_EXP_SLTSTA_MRLS),
+	FLAG(w, PCI_EXP_SLTSTA_PRSD),
+	FLAG(w, PCI_EXP_SLTSTA_LLCHG));
 }
 
 static void show_express_root(struct device *d, int where)
 {
-  u16 w = get_conf_word(d, where + PCI_EXP_RTCTL);
-  printf("\t\tRoot: Correctable%c Non-Fatal%c Fatal%c PME%c\n",
+  u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
+  printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
 	FLAG(w, PCI_EXP_RTCTL_SECEE),
 	FLAG(w, PCI_EXP_RTCTL_SENFEE),
 	FLAG(w, PCI_EXP_RTCTL_SEFEE),
-	FLAG(w, PCI_EXP_RTCTL_PMEIE));
+	FLAG(w, PCI_EXP_RTCTL_PMEIE),
+	FLAG(w, PCI_EXP_RTCTL_CRSVIS));
+
+  w = get_conf_word(d, where + PCI_EXP_RTCAP);
+  printf("\t\tRootCap: CRSVisible%c\n",
+	FLAG(w, PCI_EXP_RTCAP_CRSVIS));
+
+  w = get_conf_word(d, where + PCI_EXP_RTSTA);
+  printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
+	w & PCI_EXP_RTSTA_PME_REQID,
+	FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
+	FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
 }
 
 static void
@@ -1223,6 +1302,8 @@
   int slot = 0;
 
   printf("Express ");
+  if (verbose >= 2)
+    printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
   switch (type)
     {
     case PCI_EXP_TYPE_ENDPOINT:
@@ -1248,10 +1329,16 @@
     case PCI_EXP_TYPE_PCIE_BRIDGE:
       printf("PCI/PCI-X to PCI-Express Bridge");
       break;
+    case PCI_EXP_TYPE_ROOT_INT_EP:
+      printf("Root Complex Integrated Endpoint");
+      break;
+    case PCI_EXP_TYPE_ROOT_EC:
+      printf("Root Complex Event Collector");
+      break;
     default:
-      printf("Unknown type");
+      printf("Unknown type %d", type);
   }
-  printf(" IRQ %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+  printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
   if (verbose < 2)
     return;
 
@@ -1320,18 +1407,6 @@
 }
 
 static void
-show_aer(struct device *d UNUSED, int where UNUSED)
-{
-  printf("Advanced Error Reporting\n");
-}
-
-static void
-show_vc(struct device *d UNUSED, int where UNUSED)
-{
-  printf("Virtual Channel\n");
-}
-
-static void
 show_dsn(struct device *d, int where)
 {
   u32 t1, t2;
@@ -1345,15 +1420,11 @@
 }
 
 static void
-show_pb(struct device *d UNUSED, int where UNUSED)
-{
-  printf("Power Budgeting\n");
-}
-
-static void
 show_ext_caps(struct device *d)
 {
   int where = 0x100;
+  char been_there[0x1000];
+  memset(been_there, 0, 0x1000);
   do
     {
       u32 header;
@@ -1366,22 +1437,57 @@
 	break;
       id = header & 0xffff;
       printf("\tCapabilities: [%03x] ", where);
+      if (been_there[where++])
+	{
+	  printf("<chain looped>\n");
+	  break;
+	}
       switch (id)
 	{
 	  case PCI_EXT_CAP_ID_AER:
-	    show_aer(d, where);
+	    printf("Advanced Error Reporting\n");
+	    /* FIXME: Not decoded yet */
 	    break;
 	  case PCI_EXT_CAP_ID_VC:
-	    show_vc(d, where);
+	    printf("Virtual Channel\n");
+	    /* FIXME: Not decoded yet */
 	    break;
 	  case PCI_EXT_CAP_ID_DSN:
 	    show_dsn(d, where);
 	    break;
 	  case PCI_EXT_CAP_ID_PB:
-	    show_pb(d, where);
+	    printf("Power Budgeting\n");
+	    /* FIXME: Not decoded yet */
+	    break;
+	  case PCI_EXT_CAP_ID_RCLINK:
+	    printf("Root Complex Link\n");
+	    /* FIXME: Not decoded yet */
+	    break;
+	  case PCI_EXT_CAP_ID_RCILINK:
+	    printf("Root Complex Internal Link\n");
+	    /* FIXME: Not decoded yet */
+	    break;
+	  case PCI_EXT_CAP_ID_RCECOLL:
+	    printf("Root Complex Event Collector\n");
+	    /* FIXME: Not decoded yet */
+	    break;
+	  case PCI_EXT_CAP_ID_MFVC:
+	    printf("Multi-Function Virtual Channel\n");
+	    /* FIXME: Not decoded yet */
+	    break;
+	  case PCI_EXT_CAP_ID_RBCB:
+	    printf("Root Bridge Control Block\n");
+	    /* FIXME: Not decoded yet */
+	    break;
+	  case PCI_EXT_CAP_ID_VNDR:
+	    printf("Vendor Specific Information\n");
+	    break;
+	  case PCI_EXT_CAP_ID_ACS:
+	    printf("Access Controls\n");
+	    /* FIXME: Not decoded yet */
 	    break;
 	  default:
-	    printf("Unknown (%d)\n", id);
+	    printf("#%02x\n", id);
 	    break;
 	}
       where = header >> 20;
@@ -1396,6 +1502,8 @@
   if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
     {
       int where = get_conf_byte(d, PCI_CAPABILITY_LIST) & ~3;
+      byte been_there[256];
+      memset(been_there, 0, 256);
       while (where)
 	{
 	  int id, next, cap;
@@ -1409,6 +1517,11 @@
 	  next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
 	  cap = get_conf_word(d, where + PCI_CAP_FLAGS);
 	  printf("[%02x] ", where);
+	  if (been_there[where]++)
+	    {
+	      printf("<chain looped>\n");
+	      break;
+	    }
 	  if (id == 0xff)
 	    {
 	      printf("<chain broken>\n");
@@ -1559,14 +1672,21 @@
   show_rom(d, PCI_ROM_ADDRESS1);
 
   if (verbose > 1)
-    printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
-	   FLAG(brc, PCI_BRIDGE_CTL_PARITY),
-	   FLAG(brc, PCI_BRIDGE_CTL_SERR),
-	   FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
-	   FLAG(brc, PCI_BRIDGE_CTL_VGA),
-	   FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
-	   FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
-	   FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
+    {
+      printf("\tBridgeCtl: Parity%c SERR%c NoISA%c VGA%c MAbort%c >Reset%c FastB2B%c\n",
+	FLAG(brc, PCI_BRIDGE_CTL_PARITY),
+	FLAG(brc, PCI_BRIDGE_CTL_SERR),
+	FLAG(brc, PCI_BRIDGE_CTL_NO_ISA),
+	FLAG(brc, PCI_BRIDGE_CTL_VGA),
+	FLAG(brc, PCI_BRIDGE_CTL_MASTER_ABORT),
+	FLAG(brc, PCI_BRIDGE_CTL_BUS_RESET),
+	FLAG(brc, PCI_BRIDGE_CTL_FAST_BACK));
+      printf("\t\tPriDiscTmr%c SecDiscTmr%c DiscTmrStat%c DiscTmrSERREn%c\n",
+	FLAG(brc, PCI_BRIDGE_CTL_PRI_DISCARD_TIMER),
+	FLAG(brc, PCI_BRIDGE_CTL_SEC_DISCARD_TIMER),
+	FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS),
+	FLAG(brc, PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN));
+    }
 
   show_caps(d);
 }
@@ -1694,7 +1814,7 @@
 
   if (verbose > 1)
     {
-      printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c\n",
+      printf("\tControl: I/O%c Mem%c BusMaster%c SpecCycle%c MemWINV%c VGASnoop%c ParErr%c Stepping%c SERR%c FastB2B%c DisINTx%c\n",
 	     FLAG(cmd, PCI_COMMAND_IO),
 	     FLAG(cmd, PCI_COMMAND_MEMORY),
 	     FLAG(cmd, PCI_COMMAND_MASTER),
@@ -1704,8 +1824,9 @@
 	     FLAG(cmd, PCI_COMMAND_PARITY),
 	     FLAG(cmd, PCI_COMMAND_WAIT),
 	     FLAG(cmd, PCI_COMMAND_SERR),
-	     FLAG(cmd, PCI_COMMAND_FAST_BACK));
-      printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c\n",
+	     FLAG(cmd, PCI_COMMAND_FAST_BACK),
+	     FLAG(cmd, PCI_COMMAND_DISABLE_INTx));
+      printf("\tStatus: Cap%c 66MHz%c UDF%c FastB2B%c ParErr%c DEVSEL=%s >TAbort%c <TAbort%c <MAbort%c >SERR%c <PERR%c INTx%c\n",
 	     FLAG(status, PCI_STATUS_CAP_LIST),
 	     FLAG(status, PCI_STATUS_66MHZ),
 	     FLAG(status, PCI_STATUS_UDF),
@@ -1718,7 +1839,8 @@
 	     FLAG(status, PCI_STATUS_REC_TARGET_ABORT),
 	     FLAG(status, PCI_STATUS_REC_MASTER_ABORT),
 	     FLAG(status, PCI_STATUS_SIG_SYSTEM_ERROR),
-	     FLAG(status, PCI_STATUS_DETECTED_PARITY));
+	     FLAG(status, PCI_STATUS_DETECTED_PARITY),
+	     FLAG(status, PCI_STATUS_INTx));
       if (cmd & PCI_COMMAND_MASTER)
 	{
 	  printf("\tLatency: %d", latency);
diff -ruN pciutils-2.2.6/pciutils.lsm pciutils-2.2.7/pciutils.lsm
--- pciutils-2.2.6/pciutils.lsm	2007-06-20 20:48:06.000000000 +0200
+++ pciutils-2.2.7/pciutils.lsm	2007-10-05 14:22:33.000000000 +0200
@@ -1,14 +1,14 @@
 Begin3
 Title:          The PCI Utilities
-Version:        2.2.6
-Entered-date:   070620
+Version:        2.2.7
+Entered-date:   071005
 Description:    This package contains various utilities for inspecting and
 		setting of devices connected to the PCI bus.
 Keywords:       kernel, pci, lspci, setpci, libpci
 Author:         mj@ucw.cz (Martin Mares)
 Maintained-by:  mj@ucw.cz (Martin Mares)
-Primary-site:   atrey.karlin.mff.cuni.cz pub/linux/pci/pciutils-2.2.6.tar.gz
-Alternate-site: ftp.kernel.org pub/software/utils/pciutils/pciutils-2.2.6.tar.gz
-Alternate-site: metalab.unc.edu pub/Linux/hardware/pciutils-2.2.6.tar.gz
+Primary-site:   atrey.karlin.mff.cuni.cz pub/linux/pci/pciutils-2.2.7.tar.gz
+Alternate-site: ftp.kernel.org pub/software/utils/pciutils/pciutils-2.2.7.tar.gz
+Alternate-site: metalab.unc.edu pub/Linux/hardware/pciutils-2.2.7.tar.gz
 Copying-policy: GPL
 End
diff -ruN pciutils-2.2.6/pciutils.spec pciutils-2.2.7/pciutils.spec
--- pciutils-2.2.6/pciutils.spec	2007-06-20 20:48:06.000000000 +0200
+++ pciutils-2.2.7/pciutils.spec	2007-10-05 14:22:33.000000000 +0200
@@ -1,5 +1,5 @@
 Name:		pciutils
-Version:	2.2.6
+Version:	2.2.7
 Release: 	1
 Source:		ftp://atrey.karlin.mff.cuni.cz/pub/linux/pci/%{name}-%{version}.tar.gz
 Copyright:	GNU GPL
diff -ruN pciutils-2.2.6/tests/cap-MSI-mapping pciutils-2.2.7/tests/cap-MSI-mapping
--- pciutils-2.2.6/tests/cap-MSI-mapping	1970-01-01 01:00:00.000000000 +0100
+++ pciutils-2.2.7/tests/cap-MSI-mapping	2007-08-14 14:15:49.000000000 +0200
@@ -0,0 +1,17 @@
+0a:01.0 PCI bridge: Broadcom HT2100 PCI-Express Bridge (rev a2) (prog-if 01 [Subtractive decode])
+00: 66 11 40 01 47 00 10 00 a2 01 04 06 40 00 01 00
+10: 00 00 00 00 00 00 00 00 0a 0b 0b 00 51 51 00 20
+20: 60 ff 60 ff f1 ff 01 00 ff ff ff ff 00 00 00 00
+30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 01 01 00
+40: 00 00 00 00 01 00 01 00 01 00 00 00 00 00 01 00
+50: 08 00 a1 00 20 00 11 11 40 00 11 77 40 05 75 00
+60: 02 00 75 00 00 00 00 00 00 00 00 00 0c 05 03 03
+70: 00 00 00 00 00 00 00 00 0d 50 00 00 00 00 00 00
+80: 05 78 82 00 00 00 00 00 00 00 00 00 00 00 00 00
+90: 00 00 00 00 00 00 00 00 01 80 03 c8 08 00 00 00
+a0: 08 b0 01 a8 00 00 e0 fe 0f 00 00 00 00 00 00 00
+b0: 10 98 41 00 02 80 00 00 10 08 00 00 01 6d 1a 01
+c0: 08 00 81 20 00 00 08 00 c0 03 48 01 00 00 00 00
+d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+f0: 01 00 08 01 00 00 00 00 00 00 00 00 00 00 00 03
diff -ruN pciutils-2.2.6/win32/config.h pciutils-2.2.7/win32/config.h
--- pciutils-2.2.6/win32/config.h	2007-06-20 20:48:06.000000000 +0200
+++ pciutils-2.2.7/win32/config.h	2007-10-05 14:22:33.000000000 +0200
@@ -1,5 +1,6 @@
 #define PCI_ARCH_I386
 #define PCI_OS_WINDOWS
 #define PCI_HAVE_PM_INTEL_CONF
-#define PCI_PATH_IDS "pci.ids"
-#define PCILIB_VERSION "2.2.6"
+#define PCI_IDS "pci.ids"
+#define PCI_PATH_IDS_DIR "."
+#define PCILIB_VERSION "2.2.7"
diff -ruN pciutils-2.2.6/win32/config.mk pciutils-2.2.7/win32/config.mk
--- pciutils-2.2.6/win32/config.mk	1970-01-01 01:00:00.000000000 +0100
+++ pciutils-2.2.7/win32/config.mk	2007-09-03 10:44:16.000000000 +0200
@@ -0,0 +1,10 @@
+# TOOLPREFIX is for cross compiling
+
+CC=$(TOOLPREFIX)gcc
+LD=$(TOOLPREFIX)ld
+AR=$(TOOLPREFIX)ar
+RANLIB=$(TOOLPREFIX)ranlib
+
+PCI_ARCH_I386=yes
+PCI_OS_WINDOWS=yes
+PCI_HAVE_PM_INTEL_CONF=yes
