Chips&Media Coda multi-standard codec IP
========================================

Coda codec IPs are present in i.MX SoCs in various versions,
called VPU (Video Processing Unit).

Required properties:
- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
  (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
  (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
  (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
  (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
- reg: should be register base and length as documented in the
  SoC reference manual
- interrupts : Should contain the VPU interrupt. For CODA960,
  a second interrupt is needed for the MJPEG unit.
- clocks : Should contain the ahb and per clocks, in the order
  determined by the clock-names property.
- clock-names : Should be "ahb", "per"
- iram : phandle pointing to the SRAM device node

Example:

vpu: vpu@63ff4000 {
	compatible = "fsl,imx53-vpu";
	reg = <0x63ff4000 0x1000>;
	interrupts = <9>;
	clocks = <&clks 63>, <&clks 63>;
	clock-names = "ahb", "per";
	iram = <&ocram>;
};
