Renesas R-Car CAN controller Device Tree Bindings
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Required properties:
- compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
	      "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
	      "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
	      "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
	      "renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC.
	      "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC.
	      "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC.
	      "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
	      "renesas,can-r8a7796" if CAN controller is a part of R8A7796 SoC.
	      "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
	      "renesas,rcar-gen2-can" for a generic R-Car Gen2 compatible device.
	      "renesas,rcar-gen3-can" for a generic R-Car Gen3 compatible device.
	      When compatible with the generic version, nodes must list the
	      SoC-specific version corresponding to the platform first
	      followed by the generic version.

- reg: physical base address and size of the R-Car CAN register map.
- interrupts: interrupt specifier for the sole interrupt.
- clocks: phandles and clock specifiers for 3 CAN clock inputs.
- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk".
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must be "default".

Required properties for "renesas,can-r8a7795" and "renesas,can-r8a7796"
compatible:
In R8A7795 and R8A7796 SoCs, "clkp2" can be CANFD clock. This is a div6 clock
and can be used by both CAN and CAN FD controller at the same time. It needs to
be scaled to maximum frequency if any of these controllers use it. This is done
using the below properties:

- assigned-clocks: phandle of clkp2(CANFD) clock.
- assigned-clock-rates: maximum frequency of this clock.

Optional properties:
- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
			    <0x0> (default) : Peripheral clock (clkp1)
			    <0x1> : Peripheral clock (clkp2)
			    <0x3> : Externally input clock

Example
-------

SoC common .dtsi file:

	can0: can@e6e80000 {
		compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
		reg = <0 0xe6e80000 0 0x1000>;
		interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
		clock-names = "clkp1", "clkp2", "can_clk";
		status = "disabled";
	};

Board specific .dts file:

&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";
	status = "okay";
};
