Binding for a ST pll clock driver.

This binding uses the common clock binding[1].
Base address is located to the parent node. See clock binding[2]

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt

Required properties:

- compatible : shall be:
	"st,clkgena-prediv-c65",	"st,clkgena-prediv"
	"st,clkgena-prediv-c32",	"st,clkgena-prediv"

	"st,clkgena-plls-c65"
	"st,plls-c32-a1x-0",		"st,clkgen-plls-c32"
	"st,plls-c32-a1x-1",		"st,clkgen-plls-c32"
	"st,stih415-plls-c32-a9",	"st,clkgen-plls-c32"
	"st,stih415-plls-c32-ddr",	"st,clkgen-plls-c32"
	"st,stih416-plls-c32-a9",	"st,clkgen-plls-c32"
	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"

	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"
	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"


- #clock-cells : From common clock binding; shall be set to 1.

- clocks : From common clock binding

- clock-output-names : From common clock binding.

Example:

	clockgenA@fee62000 {
		reg = <0xfee62000 0xb48>;

		CLK_S_A0_PLL: CLK_S_A0_PLL {
			#clock-cells = <1>;
			compatible = "st,clkgena-plls-c65";

			clocks = <&CLK_SYSIN>;

			clock-output-names = "CLK_S_A0_PLL0_HS",
					     "CLK_S_A0_PLL0_LS",
					     "CLK_S_A0_PLL1";
		};
	};
