#include "upd78k2.h"
#include "util.h"
#include <stdlib.h>
#include "upd78k2_util.c"

typedef void (*impl_fun)(upd78k2_context *context, uint32_t target_cycle);
static impl_fun impl_sfr[256];
static impl_fun impl_bit1[256];
static impl_fun impl_bit2[256];
static impl_fun impl_muldiv[256];
static impl_fun impl_base[256];
static impl_fun impl_sfrbit[256];
static impl_fun impl_spmov[256];
static impl_fun impl_indexed[256];
static impl_fun impl_regind[256];
static impl_fun impl_alt_base[256];
static impl_fun impl_alt_indexed[256];
static impl_fun impl_alt_regind[256];
static impl_fun impl_mov_reg[256];
static impl_fun impl_xch_reg[256];
static impl_fun impl_shr[256];
static impl_fun impl_shl[256];
static impl_fun impl_main[256];
static void alt_base_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_alt_base[context->scratch1](context, target_cycle);
}
static void alt_indexed_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_alt_indexed[context->scratch1](context, target_cycle);
}
static void alt_regind_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_alt_regind[context->scratch1](context, target_cycle);
}
static void alu_ax_sfr_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint32_t gen_tmp32__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint8_t offset;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	offset = 1 + offset;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 16;
	context->scratch1 = tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = context->scratch1 + aluop16_ax_tmp;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ aluop16_ax_tmp ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void alu_ax_sfr_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint8_t offset;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	offset = 1 + offset;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 16;
	context->scratch1 = tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = aluop16_ax_tmp - context->scratch1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((aluop16_ax_tmp ^ context->scratch1 ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void alu_ax_sfr_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint8_t offset;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	offset = 1 + offset;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 16;
	context->scratch1 = tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = aluop16_ax_tmp - context->scratch1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((aluop16_ax_tmp ^ context->scratch1 ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void bf_psw_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 1;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_psw_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 2;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_psw_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 4;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_psw_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 8;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_psw_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 16;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_psw_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 32;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_psw_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 64;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_psw_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 128;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 1;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 2;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 4;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 8;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 16;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 32;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 64;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_psw_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	mask = context->psw & 128;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_psw_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 1 & context->psw;
	if (tmp) {
	mask = ~1;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void btclr_psw_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 2 & context->psw;
	if (tmp) {
	mask = ~2;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
	upd78k2_sync_cycle(context, target_cycle);
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void btclr_psw_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 4 & context->psw;
	if (tmp) {
	mask = ~4;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void btclr_psw_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 8 & context->psw;
	if (tmp) {
	mask = ~8;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void btclr_psw_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 16 & context->psw;
	if (tmp) {
	mask = ~16;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void btclr_psw_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 32 & context->psw;
	if (tmp) {
	mask = ~32;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void btclr_psw_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 64 & context->psw;
	if (tmp) {
	mask = ~64;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void btclr_psw_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	tmp = 128 & context->psw;
	if (tmp) {
	mask = ~128;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->psw = mask & context->psw;
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
	upd78k2_sync_cycle(context, target_cycle);
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void bf_r_B_000_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 1;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_001_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 2;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_010_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 4;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_011_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 8;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_100_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 16;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_101_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 32;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_110_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 64;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_111_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 128;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_000_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 1;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_001_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 2;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_010_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 4;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_011_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 8;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_100_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 16;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_101_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 32;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_110_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 64;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_r_B_111_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 128;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_000_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 1;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_001_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 2;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_010_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 4;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_011_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 8;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_100_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 16;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_101_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 32;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_110_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 64;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_111_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[0] & 128;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_000_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 1;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_001_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 2;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_010_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 4;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_011_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 8;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_100_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 16;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_101_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 32;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_110_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 64;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_r_B_111_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = context->main[1] & 128;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_000_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 1 & context->main[0];
	if (tmp) {
	mask = ~1;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_001_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 2 & context->main[0];
	if (tmp) {
	mask = ~2;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_010_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 4 & context->main[0];
	if (tmp) {
	mask = ~4;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_011_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 8 & context->main[0];
	if (tmp) {
	mask = ~8;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_100_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 16 & context->main[0];
	if (tmp) {
	mask = ~16;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_101_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 32 & context->main[0];
	if (tmp) {
	mask = ~32;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_110_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 64 & context->main[0];
	if (tmp) {
	mask = ~64;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_111_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 128 & context->main[0];
	if (tmp) {
	mask = ~128;
	context->main[0] = mask & context->main[0];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_000_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 1 & context->main[1];
	if (tmp) {
	mask = ~1;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_001_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 2 & context->main[1];
	if (tmp) {
	mask = ~2;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_010_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 4 & context->main[1];
	if (tmp) {
	mask = ~4;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_011_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 8 & context->main[1];
	if (tmp) {
	mask = ~8;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_100_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 16 & context->main[1];
	if (tmp) {
	mask = ~16;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_101_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 32 & context->main[1];
	if (tmp) {
	mask = ~32;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_110_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 64 & context->main[1];
	if (tmp) {
	mask = ~64;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_r_B_111_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 128 & context->main[1];
	if (tmp) {
	mask = ~128;
	context->main[1] = mask & context->main[1];
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void mulu_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[0] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void mulu_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[1] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void mulu_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[2] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void mulu_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[3] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void mulu_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[4] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void mulu_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[5] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void mulu_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[6] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void mulu_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t res;
	res = ((uint16_t)(context->main[1] & 255)) * ((uint16_t)(context->main[7] & 255));
	context->main[0] = res;
	context->main[1] = res >> 8;
	context->cycles += context->opts->gen.clock_divider * 40;
}
static void divuw_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[0] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[0] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[0] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void divuw_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[1] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[1] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[1] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void divuw_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[2] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[2] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[2] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void divuw_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[3] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[3] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[3] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void divuw_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[4] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[4] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[4] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void divuw_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[5] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[5] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[5] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void divuw_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[6] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[6] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[6] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void divuw_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t dividend;
	uint16_t quotient;
	uint16_t tmp;
	dividend = context->main[1] << 8;
	dividend = context->main[0] | dividend;
	quotient = ((uint16_t)(dividend & 255)) / ((uint16_t)(context->main[7] & 255));
	tmp = ((uint16_t)(quotient & 255)) * ((uint16_t)(context->main[7] & 255));
	context->main[0] = dividend;
	context->main[1] = dividend >> 8;
	context->main[7] = quotient - tmp;
	context->cycles += context->opts->gen.clock_divider * 144;
}
static void br_rp_P_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t reg;
	uint16_t tmp;
	context->pc = context->main[0];
	tmp = context->main[1] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void br_rp_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t reg;
	uint16_t tmp;
	context->pc = context->main[2];
	tmp = context->main[3] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void br_rp_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t reg;
	uint16_t tmp;
	context->pc = context->main[4];
	tmp = context->main[5] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void br_rp_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t reg;
	uint16_t tmp;
	context->pc = context->main[6];
	tmp = context->main[7] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void call_rp_P_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t reg;
	uint16_t tmp;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = context->main[0];
	tmp = context->main[1] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void call_rp_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t reg;
	uint16_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = context->main[2];
	tmp = context->main[3] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void call_rp_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t reg;
	uint16_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = context->main[4];
	tmp = context->main[5] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void call_rp_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t reg;
	uint16_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = context->main[6];
	tmp = context->main[7] << 8;
	context->pc = tmp | context->pc;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void sel_N_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t offset;
	if (0 != context->rbs) {
	offset = context->rbs << 3;
	offset = 248 - offset;
	context->iram[offset] = context->main[0];
	offset = 1 + offset;
	context->iram[offset] = context->main[1];
	offset = 1 + offset;
	context->iram[offset] = context->main[2];
	offset = 1 + offset;
	context->iram[offset] = context->main[3];
	offset = 1 + offset;
	context->iram[offset] = context->main[4];
	offset = 1 + offset;
	context->iram[offset] = context->main[5];
	offset = 1 + offset;
	context->iram[offset] = context->main[6];
	offset = 1 + offset;
	context->iram[offset] = context->main[7];
	offset = 0 << 3;
	offset = 248 - offset;
	context->main[0] = context->iram[offset];
	offset = 1 + offset;
	context->main[1] = context->iram[offset];
	offset = 1 + offset;
	context->main[2] = context->iram[offset];
	offset = 1 + offset;
	context->main[3] = context->iram[offset];
	offset = 1 + offset;
	context->main[4] = context->iram[offset];
	offset = 1 + offset;
	context->main[5] = context->iram[offset];
	offset = 1 + offset;
	context->main[6] = context->iram[offset];
	offset = 1 + offset;
	context->main[7] = context->iram[offset];
	context->rbs = 0;
	}
}
static void sel_N_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t offset;
	uint32_t cmp_tmp32__;
	if (1 != context->rbs) {
	offset = context->rbs << 3;
	offset = 248 - offset;
	context->iram[offset] = context->main[0];
	offset = 1 + offset;
	context->iram[offset] = context->main[1];
	offset = 1 + offset;
	context->iram[offset] = context->main[2];
	offset = 1 + offset;
	context->iram[offset] = context->main[3];
	offset = 1 + offset;
	context->iram[offset] = context->main[4];
	offset = 1 + offset;
	context->iram[offset] = context->main[5];
	offset = 1 + offset;
	context->iram[offset] = context->main[6];
	offset = 1 + offset;
	context->iram[offset] = context->main[7];
	offset = 1 << 3;
	offset = 248 - offset;
	context->main[0] = context->iram[offset];
	offset = 1 + offset;
	context->main[1] = context->iram[offset];
	offset = 1 + offset;
	context->main[2] = context->iram[offset];
	offset = 1 + offset;
	context->main[3] = context->iram[offset];
	offset = 1 + offset;
	context->main[4] = context->iram[offset];
	offset = 1 + offset;
	context->main[5] = context->iram[offset];
	offset = 1 + offset;
	context->main[6] = context->iram[offset];
	offset = 1 + offset;
	context->main[7] = context->iram[offset];
	context->rbs = 1;
	}
}
static void sel_N_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t offset;
	uint32_t cmp_tmp32__;
	if (2 != context->rbs) {
	offset = context->rbs << 3;
	offset = 248 - offset;
	context->iram[offset] = context->main[0];
	offset = 1 + offset;
	context->iram[offset] = context->main[1];
	offset = 1 + offset;
	context->iram[offset] = context->main[2];
	offset = 1 + offset;
	context->iram[offset] = context->main[3];
	offset = 1 + offset;
	context->iram[offset] = context->main[4];
	offset = 1 + offset;
	context->iram[offset] = context->main[5];
	offset = 1 + offset;
	context->iram[offset] = context->main[6];
	offset = 1 + offset;
	context->iram[offset] = context->main[7];
	offset = 2 << 3;
	offset = 248 - offset;
	context->main[0] = context->iram[offset];
	offset = 1 + offset;
	context->main[1] = context->iram[offset];
	offset = 1 + offset;
	context->main[2] = context->iram[offset];
	offset = 1 + offset;
	context->main[3] = context->iram[offset];
	offset = 1 + offset;
	context->main[4] = context->iram[offset];
	offset = 1 + offset;
	context->main[5] = context->iram[offset];
	offset = 1 + offset;
	context->main[6] = context->iram[offset];
	offset = 1 + offset;
	context->main[7] = context->iram[offset];
	context->rbs = 2;
	}
}
static void sel_N_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t offset;
	uint32_t cmp_tmp32__;
	if (3 != context->rbs) {
	offset = context->rbs << 3;
	offset = 248 - offset;
	context->iram[offset] = context->main[0];
	offset = 1 + offset;
	context->iram[offset] = context->main[1];
	offset = 1 + offset;
	context->iram[offset] = context->main[2];
	offset = 1 + offset;
	context->iram[offset] = context->main[3];
	offset = 1 + offset;
	context->iram[offset] = context->main[4];
	offset = 1 + offset;
	context->iram[offset] = context->main[5];
	offset = 1 + offset;
	context->iram[offset] = context->main[6];
	offset = 1 + offset;
	context->iram[offset] = context->main[7];
	offset = 3 << 3;
	offset = 248 - offset;
	context->main[0] = context->iram[offset];
	offset = 1 + offset;
	context->main[1] = context->iram[offset];
	offset = 1 + offset;
	context->main[2] = context->iram[offset];
	offset = 1 + offset;
	context->main[3] = context->iram[offset];
	offset = 1 + offset;
	context->main[4] = context->iram[offset];
	offset = 1 + offset;
	context->main[5] = context->iram[offset];
	offset = 1 + offset;
	context->main[6] = context->iram[offset];
	offset = 1 + offset;
	context->main[7] = context->iram[offset];
	context->rbs = 3;
	}
}
static void incw_sp(upd78k2_context *context, uint32_t target_cycle)
{
	context->sp = 1 + context->sp;
}
static void decw_sp(upd78k2_context *context, uint32_t target_cycle)
{
	context->sp = context->sp - 1;
}
static void movw_ax_mem_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t address;
	uint8_t reg;
	address = context->main[5] << 8;
	address = context->main[4] | address;
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = address | mem_read_full_address;
	} else {
	mem_read_full_address = address;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[0] = context->scratch1;
	address = 1 + address;
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = address | mem_read_full_address;
	} else {
	mem_read_full_address = address;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void movw_ax_mem_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t address;
	uint8_t reg;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	address = context->main[7] << 8;
	address = context->main[6] | address;
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = address | mem_read_full_address;
	} else {
	mem_read_full_address = address;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[0] = context->scratch1;
	address = 1 + address;
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = address | mem_read_full_address;
	} else {
	mem_read_full_address = address;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void movw_mem_ax_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t reg;
	address = context->main[5] << 8;
	address = context->main[4] | address;
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = address | mem_write_full_address;
	} else {
	mem_write_full_address = address;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[0];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[0];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[0];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[0];
	upd78k2_write_8(context);
	}
	address = 1 + address;
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = address | mem_write_full_address;
	} else {
	mem_write_full_address = address;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void movw_mem_ax_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t reg;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	address = context->main[7] << 8;
	address = context->main[6] | address;
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = address | mem_write_full_address;
	} else {
	mem_write_full_address = address;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[0];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[0];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[0];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[0];
	upd78k2_write_8(context);
	}
	address = 1 + address;
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = address | mem_write_full_address;
	} else {
	mem_write_full_address = address;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_a_base_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_base_P_000_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_001_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_010_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_011_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_100_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_101_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_110_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_111_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_base_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_base_P_000_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_001_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_010_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_011_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_100_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_101_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_110_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_111_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_base_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_base_P_000_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_001_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_010_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_011_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_base_P_100_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_101_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_110_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_base_P_111_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_base_a_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch2 & 65535);
	context->scratch2 = (context->scratch2 & ~65535) | gen_tmp16__;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_base_a_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch2 & 65535);
	context->scratch2 = (context->scratch2 & ~65535) | gen_tmp16__;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_base_a_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch2 & 65535);
	context->scratch2 = (context->scratch2 & ~65535) | gen_tmp16__;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov1_cy_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 1 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 2 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 4 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 8 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 16 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 32 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 64 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 128 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 1 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 2 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 4 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 8 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 16 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 32 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 64 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_cy_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 128 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
}
static void mov1_saddr_cy_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 1 | context->scratch1;
	} else {
	mask = ~1;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_saddr_cy_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 2 | context->scratch1;
	} else {
	mask = ~2;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_saddr_cy_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 4 | context->scratch1;
	} else {
	mask = ~4;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_saddr_cy_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 8 | context->scratch1;
	} else {
	mask = ~8;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_saddr_cy_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 16 | context->scratch1;
	} else {
	mask = ~16;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_saddr_cy_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 32 | context->scratch1;
	} else {
	mask = ~32;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_saddr_cy_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 64 | context->scratch1;
	} else {
	mask = ~64;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_saddr_cy_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	if (context->chflags >= 128) {
	context->scratch1 = 128 | context->scratch1;
	} else {
	mask = ~128;
	context->scratch1 = mask & context->scratch1;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov1_sfr_cy_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 1 | context->scratch1;
	} else {
	mask = ~1;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void mov1_sfr_cy_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 2 | context->scratch1;
	} else {
	mask = ~2;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void mov1_sfr_cy_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 4 | context->scratch1;
	} else {
	mask = ~4;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void mov1_sfr_cy_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 8 | context->scratch1;
	} else {
	mask = ~8;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void mov1_sfr_cy_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 16 | context->scratch1;
	} else {
	mask = ~16;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void mov1_sfr_cy_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 32 | context->scratch1;
	} else {
	mask = ~32;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void mov1_sfr_cy_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 64 | context->scratch1;
	} else {
	mask = ~64;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void mov1_sfr_cy_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	if (context->chflags >= 128) {
	context->scratch1 = 128 | context->scratch1;
	} else {
	mask = ~128;
	context->scratch1 = mask & context->scratch1;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void and1_cy_saddr_B_000_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 1 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_001_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 2 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_010_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 4 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_011_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 8 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_100_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 16 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_101_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 32 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_110_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 64 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_111_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 128 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_000_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 1 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_001_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 2 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_010_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 4 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_011_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 8 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_100_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 16 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_101_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 32 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_110_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 64 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_111_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 128 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_000_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 1 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_001_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 2 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_010_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 4 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_011_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 8 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_100_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 16 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_101_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 32 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_110_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 64 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_saddr_B_111_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 128 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_000_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 1 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_001_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 2 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_010_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 4 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_011_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 8 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_100_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 16 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_101_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 32 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_110_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 64 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void and1_cy_sfr_B_111_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 128 & context->scratch1;
	if (!context->scratch1) {
	context->chflags &= ~128;
	}
}
static void or1_cy_saddr_B_000_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 1 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_001_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 2 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_010_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 4 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_011_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 8 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_100_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 16 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_101_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 32 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_110_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 64 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_111_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 128 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_000_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 1 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_001_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 2 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_010_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 4 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_011_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 8 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_100_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 16 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_101_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 32 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_110_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 64 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_111_I_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 128 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_000_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 1 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_001_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 2 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_010_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 4 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_011_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 8 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_100_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 16 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_101_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 32 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_110_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 64 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_saddr_B_111_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 128 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_000_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 1 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_001_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 2 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_010_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 4 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_011_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 8 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_100_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 16 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_101_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 32 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_110_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 64 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void or1_cy_sfr_B_111_I_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = ~context->scratch1;
	context->scratch1 = 128 & context->scratch1;
	if (context->scratch1) {
	context->chflags |= 128;
	}
}
static void xor1_cy_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 1 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 2 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 4 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 8 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 16 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 32 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 64 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 128 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 1 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 2 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 4 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 8 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 16 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 32 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 64 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void xor1_cy_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 128 & context->scratch1;
	if (context->scratch1) {
	if (context->chflags >= 128) {
	context->chflags &= ~128;
	} else {
	context->chflags |= 128;
	}
	}
}
static void not1_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 1 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 2 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 4 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 8 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 16 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 32 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 64 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 128 ^ context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void not1_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 1 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void not1_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 2 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void not1_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 4 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void not1_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 8 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void not1_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 16 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void not1_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 32 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void not1_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 64 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void not1_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 128 ^ context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 1 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 2 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 4 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 8 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 16 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 32 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 64 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void set1_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = 128 | context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -2 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -3 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -5 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -9 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -17 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -33 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -65 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void clr1_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->scratch1 = -129 & context->scratch1;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void bf_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 1;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 2;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 4;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 8;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 16;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 32;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 64;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 128;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 1;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 2;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 4;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 8;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 16;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 32;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 64;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bf_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 128;
	if (!mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 1;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 2;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 4;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 8;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 16;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 32;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 64;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 128;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 1 & value;
	if (tmp) {
	mask = ~1;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 2 & value;
	if (tmp) {
	mask = ~2;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 4 & value;
	if (tmp) {
	mask = ~4;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 8 & value;
	if (tmp) {
	mask = ~8;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 16 & value;
	if (tmp) {
	mask = ~16;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 32 & value;
	if (tmp) {
	mask = ~32;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 64 & value;
	if (tmp) {
	mask = ~64;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 128 & value;
	if (tmp) {
	mask = ~128;
	value = mask & value;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = value;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = value;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	}
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 1 & value;
	if (tmp) {
	mask = ~1;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 2 & value;
	if (tmp) {
	mask = ~2;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 4 & value;
	if (tmp) {
	mask = ~4;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 8 & value;
	if (tmp) {
	mask = ~8;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 16 & value;
	if (tmp) {
	mask = ~16;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 32 & value;
	if (tmp) {
	mask = ~32;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 64 & value;
	if (tmp) {
	mask = ~64;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void btclr_sfr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t offset;
	uint8_t value;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	value = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = 128 & value;
	if (tmp) {
	mask = ~128;
	value = mask & value;
	context->scratch2 = offset + 65280;
	context->scratch1 = value;
	upd78k2_write_8(context);
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void mov_stbc_immed(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	tmp = ~context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (tmp == context->scratch1) {
	context->stbc = tmp;
	}
}
static void mov_a_abs(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	if (context->scratch1 >= 65024) {
	if (context->scratch1 >= 65280) {
	mem_read_no_exp_offset = context->scratch1;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->scratch1;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->scratch1;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void mov_abs_a(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	context->scratch2 = context->scratch1;
	if (context->scratch2 >= 65024) {
	if (context->scratch2 >= 65280) {
	mem_write_no_exp_offset = context->scratch2;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->scratch2;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->scratch2;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_a_indexed_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_indexed_P_000_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_indexed_P_001_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_010_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_011_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_100_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_101_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_110_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_111_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_indexed_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_indexed_P_000_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_001_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_010_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_011_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_100_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_101_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_110_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_111_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_indexed_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_indexed_P_000_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_001_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_010_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_011_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_100_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_101_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_110_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_111_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_indexed_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_indexed_P_000_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_001_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_010_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_011_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_indexed_P_100_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_101_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_110_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_indexed_P_111_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_indexed_a_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch2 = calc_addr_indexed_tmp + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_indexed_a_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch2 = context->main[1] + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_indexed_a_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch2 = calc_addr_indexed_tmp + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_indexed_a_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch2 = context->main[3] + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_a_reg_indirect_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_reg_indirect_P_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_reg_indirect_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_reg_indirect_P_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_reg_indirect_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_reg_indirect_P_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_reg_indirect_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_reg_indirect_P_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_reg_indirect_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_reg_indirect_P_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_a_reg_indirect_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_reg_indirect_P_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_reg_indirect_P_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_reg_indirect_P_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void mov_reg_indirect_a_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_a_base_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_base_P_000_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_001_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_010_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_011_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_100_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_101_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_110_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_111_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_base_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_base_P_000_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_001_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_010_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_011_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_100_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_101_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_110_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_111_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_base_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_base_P_000_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_001_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_010_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_011_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_base_P_100_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_101_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_110_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_base_P_111_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch1 & 65535);
	context->scratch1 = (context->scratch1 & ~65535) | gen_tmp16__;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_base_a_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[5] << 8;
	calc_addr_base_tmp = context->main[4] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch2 & 65535);
	context->scratch2 = (context->scratch2 & ~65535) | gen_tmp16__;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_base_a_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 & 255;
	{
	gen_tmp16__ = (context->sp & 65535) + (context->scratch2 & 65535);
	context->scratch2 = (context->scratch2 & ~65535) | gen_tmp16__;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_base_a_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_base_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 & 255;
	{
	calc_addr_base_tmp = context->main[7] << 8;
	calc_addr_base_tmp = context->main[6] | calc_addr_base_tmp;
	gen_tmp16__ = (calc_addr_base_tmp & 65535) + (context->scratch2 & 65535);
	context->scratch2 = (context->scratch2 & ~65535) | gen_tmp16__;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_a_indexed_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_indexed_P_000_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = (context->main[1] & ~65535) | (gen_tmp16__ & 65535);
	}
}
static void alu_alt_indexed_P_001_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_010_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_011_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_100_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_101_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_110_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_111_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_indexed_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_indexed_P_000_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_001_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_010_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_011_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_100_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_101_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_110_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_111_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[1] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_indexed_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_indexed_P_000_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_001_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_010_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_011_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_100_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_101_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_110_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_111_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch1 = calc_addr_indexed_tmp + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_indexed_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_indexed_P_000_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_001_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_010_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_011_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_indexed_P_100_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_101_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_110_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_indexed_P_111_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch1 = context->main[3] + context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_indexed_a_R_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[5] << 8;
	calc_addr_indexed_tmp = context->main[4] | calc_addr_indexed_tmp;
	context->scratch2 = calc_addr_indexed_tmp + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_indexed_a_R_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch2 = context->main[1] + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_indexed_a_R_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	calc_addr_indexed_tmp = context->main[7] << 8;
	calc_addr_indexed_tmp = context->main[6] | calc_addr_indexed_tmp;
	context->scratch2 = calc_addr_indexed_tmp + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_indexed_a_R_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_indexed_tmp;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	{
	context->scratch2 = context->main[3] + context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_a_reg_indirect_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_reg_indirect_P_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_reg_indirect_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_reg_indirect_P_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_reg_indirect_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_reg_indirect_P_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_reg_indirect_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_reg_indirect_P_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_reg_indirect_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_reg_indirect_P_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_a_reg_indirect_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_alt_reg_indirect_P_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_alt_reg_indirect_P_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_alt_reg_indirect_P_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t cmp_tmp16__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_data[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void alt_mov_reg_indirect_a_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_reg_indirect_a_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_reg_indirect_a_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_reg_indirect_a_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_reg_indirect_a_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void alt_mov_reg_indirect_a_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_data[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_r_r_D_000_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[0];
}
static void mov_r_r_D_000_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[1];
}
static void mov_r_r_D_000_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[2];
}
static void mov_r_r_D_000_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[3];
}
static void mov_r_r_D_000_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[4];
}
static void mov_r_r_D_000_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[5];
}
static void mov_r_r_D_000_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[6];
}
static void mov_r_r_D_000_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[0] = context->main[7];
}
static void movw_rp_rp_D_00_S_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[0] = context->main[0];
	context->main[1] = context->main[1];
}
static void movw_rp_rp_D_00_S_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[0] = context->main[2];
	context->main[1] = context->main[3];
}
static void movw_rp_rp_D_00_S_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[0] = context->main[4];
	context->main[1] = context->main[5];
}
static void movw_rp_rp_D_00_S_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[0] = context->main[6];
	context->main[1] = context->main[7];
}
static void mov_r_r_D_001_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[0];
}
static void mov_r_r_D_001_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[1];
}
static void mov_r_r_D_001_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[2];
}
static void mov_r_r_D_001_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[3];
}
static void mov_r_r_D_001_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[4];
}
static void mov_r_r_D_001_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[5];
}
static void mov_r_r_D_001_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[6];
}
static void mov_r_r_D_001_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[7];
}
static void mov_r_r_D_010_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[0];
}
static void mov_r_r_D_010_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[1];
}
static void mov_r_r_D_010_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[2];
}
static void mov_r_r_D_010_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[3];
}
static void mov_r_r_D_010_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[4];
}
static void mov_r_r_D_010_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[5];
}
static void mov_r_r_D_010_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[6];
}
static void mov_r_r_D_010_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[2] = context->main[7];
}
static void movw_rp_rp_D_01_S_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[2] = context->main[0];
	context->main[3] = context->main[1];
}
static void movw_rp_rp_D_01_S_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[2] = context->main[2];
	context->main[3] = context->main[3];
}
static void movw_rp_rp_D_01_S_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[2] = context->main[4];
	context->main[3] = context->main[5];
}
static void movw_rp_rp_D_01_S_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[2] = context->main[6];
	context->main[3] = context->main[7];
}
static void mov_r_r_D_011_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[0];
}
static void mov_r_r_D_011_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[1];
}
static void mov_r_r_D_011_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[2];
}
static void mov_r_r_D_011_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[3];
}
static void mov_r_r_D_011_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[4];
}
static void mov_r_r_D_011_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[5];
}
static void mov_r_r_D_011_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[6];
}
static void mov_r_r_D_011_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[3] = context->main[7];
}
static void mov_r_r_D_100_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[0];
}
static void mov_r_r_D_100_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[1];
}
static void mov_r_r_D_100_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[2];
}
static void mov_r_r_D_100_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[3];
}
static void mov_r_r_D_100_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[4];
}
static void mov_r_r_D_100_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[5];
}
static void mov_r_r_D_100_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[6];
}
static void mov_r_r_D_100_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[4] = context->main[7];
}
static void movw_rp_rp_D_10_S_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[4] = context->main[0];
	context->main[5] = context->main[1];
}
static void movw_rp_rp_D_10_S_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[4] = context->main[2];
	context->main[5] = context->main[3];
}
static void movw_rp_rp_D_10_S_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[4] = context->main[4];
	context->main[5] = context->main[5];
}
static void movw_rp_rp_D_10_S_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[4] = context->main[6];
	context->main[5] = context->main[7];
}
static void mov_r_r_D_101_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[0];
}
static void mov_r_r_D_101_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[1];
}
static void mov_r_r_D_101_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[2];
}
static void mov_r_r_D_101_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[3];
}
static void mov_r_r_D_101_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[4];
}
static void mov_r_r_D_101_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[5];
}
static void mov_r_r_D_101_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[6];
}
static void mov_r_r_D_101_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[5] = context->main[7];
}
static void mov_r_r_D_110_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[0];
}
static void mov_r_r_D_110_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[1];
}
static void mov_r_r_D_110_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[2];
}
static void mov_r_r_D_110_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[3];
}
static void mov_r_r_D_110_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[4];
}
static void mov_r_r_D_110_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[5];
}
static void mov_r_r_D_110_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[6];
}
static void mov_r_r_D_110_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[6] = context->main[7];
}
static void movw_rp_rp_D_11_S_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[6] = context->main[0];
	context->main[7] = context->main[1];
}
static void movw_rp_rp_D_11_S_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[6] = context->main[2];
	context->main[7] = context->main[3];
}
static void movw_rp_rp_D_11_S_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[6] = context->main[4];
	context->main[7] = context->main[5];
}
static void movw_rp_rp_D_11_S_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t dst;
	uint8_t src;
	context->main[6] = context->main[6];
	context->main[7] = context->main[7];
}
static void mov_r_r_D_111_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[0];
}
static void mov_r_r_D_111_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[1];
}
static void mov_r_r_D_111_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[2];
}
static void mov_r_r_D_111_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[3];
}
static void mov_r_r_D_111_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[4];
}
static void mov_r_r_D_111_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[5];
}
static void mov_r_r_D_111_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[6];
}
static void mov_r_r_D_111_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[7] = context->main[7];
}
static void xch_r_r_D_000_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_000_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_000_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_000_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_000_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_000_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_000_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_000_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[0];
	context->main[0] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void xch_r_r_D_001_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_001_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_001_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_001_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_001_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_001_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_001_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_001_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void xch_r_r_D_010_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_010_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_010_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_010_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_010_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_010_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_010_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_010_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[2];
	context->main[2] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void xch_r_r_D_011_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_011_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_011_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_011_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_011_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_011_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_011_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_011_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[3];
	context->main[3] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void xch_r_r_D_100_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_100_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_100_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_100_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_100_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_100_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_100_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_100_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[4];
	context->main[4] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void xch_r_r_D_101_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_101_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_101_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_101_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_101_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_101_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_101_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_101_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[5];
	context->main[5] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void xch_r_r_D_110_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_110_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_110_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_110_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_110_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_110_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_110_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_110_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[6];
	context->main[6] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void xch_r_r_D_111_S_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_r_r_D_111_S_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_r_r_D_111_S_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_r_r_D_111_S_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_r_r_D_111_S_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_r_r_D_111_S_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_r_r_D_111_S_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_r_r_D_111_S_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[7];
	context->main[7] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void rorc_r_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 0 | context->main[0] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 0 | context->main[1] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 0 | context->main[2] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 0 | context->main[3] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 0 | context->main[4] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 0 | context->main[5] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 0 | context->main[6] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 0 | context->main[7] << (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-0);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rorc_r_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 1 | context->main[0] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 1 | context->main[1] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 1 | context->main[2] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 1 | context->main[3] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 1 | context->main[4] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 1 | context->main[5] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 1 | context->main[6] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 1 | context->main[7] << (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rorc_r_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 2 | context->main[0] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 6U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 2 | context->main[1] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 6U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 2 | context->main[2] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 6U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 2 | context->main[3] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 6U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 2 | context->main[4] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 6U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 2 | context->main[5] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 6U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 2 | context->main[6] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 6U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 2 | context->main[7] << (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-2);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 6U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rorc_r_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 3 | context->main[0] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 5U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 3 | context->main[1] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 5U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 3 | context->main[2] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 5U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 3 | context->main[3] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 5U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 3 | context->main[4] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 5U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 3 | context->main[5] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 5U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 3 | context->main[6] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 5U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 3 | context->main[7] << (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-3);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 5U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rorc_r_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 4 | context->main[0] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 4U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 4 | context->main[1] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 4U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 4 | context->main[2] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 4U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 4 | context->main[3] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 4U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 4 | context->main[4] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 4U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 4 | context->main[5] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 4U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 4 | context->main[6] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 4U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 4 | context->main[7] << (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-4);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 4U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rorc_r_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 5 | context->main[0] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 3U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 5 | context->main[1] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 3U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 5 | context->main[2] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 3U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 5 | context->main[3] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 3U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 5 | context->main[4] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 3U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 5 | context->main[5] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 3U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 5 | context->main[6] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 3U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 5 | context->main[7] << (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-5);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 3U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rorc_r_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 6 | context->main[0] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 2U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 6 | context->main[1] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 2U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 6 | context->main[2] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 2U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 6 | context->main[3] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 2U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 6 | context->main[4] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 2U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 6 | context->main[5] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 2U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 6 | context->main[6] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 2U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 6 | context->main[7] << (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-6);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 2U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rorc_r_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 7 | context->main[0] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 1U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rorc_r_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 7 | context->main[1] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 1U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rorc_r_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 7 | context->main[2] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 1U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rorc_r_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 7 | context->main[3] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 1U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rorc_r_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 7 | context->main[4] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 1U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rorc_r_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 7 | context->main[5] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 1U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rorc_r_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 7 | context->main[6] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 1U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rorc_r_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 7 | context->main[7] << (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (8-7);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 1U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 0 | context->main[0] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 0 | context->main[1] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 0 | context->main[2] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 0 | context->main[3] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 0 | context->main[4] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 0 | context->main[5] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 0 | context->main[6] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 0 | context->main[7] << (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void ror_r_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 1 | context->main[0] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 1 | context->main[1] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 1 | context->main[2] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 1 | context->main[3] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 1 | context->main[4] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 1 | context->main[5] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 1 | context->main[6] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 1 | context->main[7] << (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void ror_r_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 2 | context->main[0] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 2 | context->main[1] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 2 | context->main[2] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 2 | context->main[3] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 2 | context->main[4] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 2 | context->main[5] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 2 | context->main[6] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 2 | context->main[7] << (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void ror_r_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 3 | context->main[0] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 3 | context->main[1] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 3 | context->main[2] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 3 | context->main[3] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 3 | context->main[4] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 3 | context->main[5] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 3 | context->main[6] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 3 | context->main[7] << (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void ror_r_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 4 | context->main[0] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 4 | context->main[1] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 4 | context->main[2] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 4 | context->main[3] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 4 | context->main[4] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 4 | context->main[5] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 4 | context->main[6] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 4 | context->main[7] << (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void ror_r_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 5 | context->main[0] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 5 | context->main[1] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 5 | context->main[2] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 5 | context->main[3] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 5 | context->main[4] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 5 | context->main[5] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 5 | context->main[6] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 5 | context->main[7] << (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void ror_r_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 6 | context->main[0] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 6 | context->main[1] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 6 | context->main[2] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 6 | context->main[3] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 6 | context->main[4] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 6 | context->main[5] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 6 | context->main[6] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 6 | context->main[7] << (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void ror_r_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] >> 7 | context->main[0] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] >> 7 | context->main[1] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] >> 7 | context->main[2] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] >> 7 | context->main[3] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] >> 7 | context->main[4] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] >> 7 | context->main[5] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] >> 7 | context->main[6] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void ror_r_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] >> 7 | context->main[7] << (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 0;
	context->zflag = gen_tmp8__ == 0;
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shr_r_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shr_r_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 6U & 128U);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 6U & 128U);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 6U & 128U);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 6U & 128U);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 6U & 128U);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 6U & 128U);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 6U & 128U);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 2;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 6U & 128U);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shr_r_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 5U & 128U);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 5U & 128U);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 5U & 128U);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 5U & 128U);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 5U & 128U);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 5U & 128U);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 5U & 128U);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 3;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 5U & 128U);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shr_r_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 4U & 128U);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 4U & 128U);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 4U & 128U);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 4U & 128U);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 4U & 128U);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 4U & 128U);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 4U & 128U);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 4;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 4U & 128U);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shr_r_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 3U & 128U);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 3U & 128U);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 3U & 128U);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 3U & 128U);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 3U & 128U);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 3U & 128U);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 3U & 128U);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 5;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 3U & 128U);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shr_r_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 2U & 128U);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 2U & 128U);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 2U & 128U);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 2U & 128U);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 2U & 128U);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 2U & 128U);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 2U & 128U);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 6;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 2U & 128U);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shr_r_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 1U & 128U);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 1U & 128U);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 1U & 128U);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 1U & 128U);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 1U & 128U);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 1U & 128U);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 1U & 128U);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shr_r_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] >> 7;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 1U & 128U);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shrw_rp_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 0;
	context->zflag = gen_tmp16__ == 0;
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shrw_rp_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 7U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shrw_rp_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 2;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 6U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shrw_rp_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 3;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 5U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shrw_rp_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 4;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 4U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shrw_rp_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 5;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 3U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shrw_rp_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 6;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 2U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shrw_rp_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shrw_rp_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shrw_rp_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shrw_rp_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shrw_rp_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shrw_rp_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shrw_rp_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shrw_rp_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp16__ = tmp >> 7;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~128U) | (tmp << 1U & 128U);
	tmp = gen_tmp16__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void rolc_r_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 0 | context->main[0] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[0] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 0 | context->main[1] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[1] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 0 | context->main[2] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[2] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 0 | context->main[3] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[3] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 0 | context->main[4] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[4] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 0 | context->main[5] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[5] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 0 | context->main[6] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[6] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 0 | context->main[7] >> (8 + 1 - 0) | ((context->chflags & 1 << 7) ? 1 : 0) << (0 - 1);
	context->main[7] = gen_tmp8__;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rolc_r_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 1 | context->main[0] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 1 | context->main[1] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 1 | context->main[2] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 1 | context->main[3] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 1 | context->main[4] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 1 | context->main[5] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 1 | context->main[6] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 1 | context->main[7] >> (8 + 1 - 1) | ((context->chflags & 1 << 7) ? 1 : 0) << (1 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rolc_r_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 2 | context->main[0] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 1U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 2 | context->main[1] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 1U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 2 | context->main[2] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 1U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 2 | context->main[3] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 1U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 2 | context->main[4] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 1U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 2 | context->main[5] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 1U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 2 | context->main[6] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 1U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 2 | context->main[7] >> (8 + 1 - 2) | ((context->chflags & 1 << 7) ? 1 : 0) << (2 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 1U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rolc_r_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 3 | context->main[0] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 2U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 3 | context->main[1] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 2U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 3 | context->main[2] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 2U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 3 | context->main[3] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 2U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 3 | context->main[4] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 2U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 3 | context->main[5] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 2U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 3 | context->main[6] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 2U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 3 | context->main[7] >> (8 + 1 - 3) | ((context->chflags & 1 << 7) ? 1 : 0) << (3 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 2U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rolc_r_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 4 | context->main[0] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 3U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 4 | context->main[1] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 3U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 4 | context->main[2] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 3U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 4 | context->main[3] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 3U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 4 | context->main[4] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 3U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 4 | context->main[5] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 3U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 4 | context->main[6] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 3U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 4 | context->main[7] >> (8 + 1 - 4) | ((context->chflags & 1 << 7) ? 1 : 0) << (4 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 3U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rolc_r_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 5 | context->main[0] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 4U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 5 | context->main[1] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 4U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 5 | context->main[2] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 4U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 5 | context->main[3] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 4U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 5 | context->main[4] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 4U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 5 | context->main[5] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 4U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 5 | context->main[6] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 4U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 5 | context->main[7] >> (8 + 1 - 5) | ((context->chflags & 1 << 7) ? 1 : 0) << (5 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 4U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rolc_r_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 6 | context->main[0] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 5U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 6 | context->main[1] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 5U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 6 | context->main[2] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 5U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 6 | context->main[3] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 5U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 6 | context->main[4] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 5U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 6 | context->main[5] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 5U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 6 | context->main[6] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 5U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 6 | context->main[7] >> (8 + 1 - 6) | ((context->chflags & 1 << 7) ? 1 : 0) << (6 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 5U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rolc_r_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[0] << 7 | context->main[0] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 6U & 128U);
	context->main[0] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rolc_r_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[1] << 7 | context->main[1] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 6U & 128U);
	context->main[1] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rolc_r_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[2] << 7 | context->main[2] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 6U & 128U);
	context->main[2] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rolc_r_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[3] << 7 | context->main[3] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 6U & 128U);
	context->main[3] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rolc_r_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[4] << 7 | context->main[4] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 6U & 128U);
	context->main[4] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rolc_r_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[5] << 7 | context->main[5] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 6U & 128U);
	context->main[5] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rolc_r_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[6] << 7 | context->main[6] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 6U & 128U);
	context->main[6] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rolc_r_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	uint32_t cyc;
	gen_tmp8__ = context->main[7] << 7 | context->main[7] >> (8 + 1 - 7) | ((context->chflags & 1 << 7) ? 1 : 0) << (7 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 6U & 128U);
	context->main[7] = gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 0 | context->main[0] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 0 | context->main[1] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 0 | context->main[2] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 0 | context->main[3] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 0 | context->main[4] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 0 | context->main[5] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 0 | context->main[6] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 0 | context->main[7] >> (8 - 0);
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void rol_r_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 1 | context->main[0] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 1 | context->main[1] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 1 | context->main[2] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 1 | context->main[3] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 1 | context->main[4] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 1 | context->main[5] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 1 | context->main[6] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 1 | context->main[7] >> (8 - 1);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void rol_r_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 2 | context->main[0] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 2 | context->main[1] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 2 | context->main[2] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 2 | context->main[3] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 2 | context->main[4] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 2 | context->main[5] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 2 | context->main[6] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 2 | context->main[7] >> (8 - 2);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void rol_r_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 3 | context->main[0] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 3 | context->main[1] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 3 | context->main[2] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 3 | context->main[3] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 3 | context->main[4] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 3 | context->main[5] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 3 | context->main[6] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 3 | context->main[7] >> (8 - 3);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void rol_r_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 4 | context->main[0] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 4 | context->main[1] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 4 | context->main[2] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 4 | context->main[3] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 4 | context->main[4] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 4 | context->main[5] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 4 | context->main[6] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 4 | context->main[7] >> (8 - 4);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void rol_r_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 5 | context->main[0] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 5 | context->main[1] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 5 | context->main[2] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 5 | context->main[3] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 5 | context->main[4] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 5 | context->main[5] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 5 | context->main[6] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 5 | context->main[7] >> (8 - 5);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void rol_r_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 6 | context->main[0] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 6 | context->main[1] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 6 | context->main[2] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 6 | context->main[3] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 6 | context->main[4] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 6 | context->main[5] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 6 | context->main[6] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 6 | context->main[7] >> (8 - 6);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void rol_r_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[0] = context->main[0] << 7 | context->main[0] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[0] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[1] = context->main[1] << 7 | context->main[1] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[1] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[2] = context->main[2] << 7 | context->main[2] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[2] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[3] = context->main[3] << 7 | context->main[3] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[3] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[4] = context->main[4] << 7 | context->main[4] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[4] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[5] = context->main[5] << 7 | context->main[5] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[5] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[6] = context->main[6] << 7 | context->main[6] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[6] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void rol_r_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cyc;
	context->main[7] = context->main[7] << 7 | context->main[7] >> (8 - 7);
	context->chflags = (context->chflags & ~128U) | (context->main[7] << 7U & 128U);
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 0;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shl_r_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void shl_r_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 2;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 10;
}
static void shl_r_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 3;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shl_r_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 4;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void shl_r_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 5;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 22;
}
static void shl_r_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 6;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shl_r_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[0] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[0] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[1] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[1] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[2] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[2] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[3] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[3] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[4] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[4] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[5] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[5] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[6] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[6] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shl_r_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint32_t cyc;
	gen_tmp16__ = context->main[7] << 7;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->main[7] = gen_tmp16__;
	context->chflags &= ~8;
	context->cycles += context->opts->gen.clock_divider * 30;
}
static void shlw_rp_N_000_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_000_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_000_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_000_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_000_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_000_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_000_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_000_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 0;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->chflags &= ~128;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void shlw_rp_N_001_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_001_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_001_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_001_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_001_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_001_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_001_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_001_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 8;
}
static void shlw_rp_N_010_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_010_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_010_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_010_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_010_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_010_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_010_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_010_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 2;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 14;
}
static void shlw_rp_N_011_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_011_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_011_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_011_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_011_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_011_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_011_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_011_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 3;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 20;
}
static void shlw_rp_N_100_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_100_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_100_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_100_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_100_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_100_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_100_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_100_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 4;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 26;
}
static void shlw_rp_N_101_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_101_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_101_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_101_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_101_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_101_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_101_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_101_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 5;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 32;
}
static void shlw_rp_N_110_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_110_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_110_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_110_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_110_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_110_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_110_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_110_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 6;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 38;
}
static void shlw_rp_N_111_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[1] << 8;
	tmp = context->main[0] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[0] = tmp;
	context->main[1] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shlw_rp_N_111_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[2] << 8;
	tmp = context->main[1] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[1] = tmp;
	context->main[2] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shlw_rp_N_111_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[3] << 8;
	tmp = context->main[2] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[2] = tmp;
	context->main[3] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shlw_rp_N_111_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[4] << 8;
	tmp = context->main[3] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[3] = tmp;
	context->main[4] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shlw_rp_N_111_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[5] << 8;
	tmp = context->main[4] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[4] = tmp;
	context->main[5] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shlw_rp_N_111_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[6] << 8;
	tmp = context->main[5] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[5] = tmp;
	context->main[6] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shlw_rp_N_111_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[7] << 8;
	tmp = context->main[6] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[6] = tmp;
	context->main[7] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void shlw_rp_N_111_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint32_t cyc;
	uint8_t reg;
	uint16_t tmp;
	tmp = context->main[8] << 8;
	tmp = context->main[7] | tmp;
	gen_tmp32__ = tmp << 7;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	tmp = gen_tmp32__;
	context->chflags &= ~8;
	context->main[7] = tmp;
	context->main[8] = tmp >> 8;
	context->cycles += context->opts->gen.clock_divider * 44;
}
static void nop(upd78k2_context *context, uint32_t target_cycle)
{
	context->cycles += context->opts->gen.clock_divider * 2;
}
static void sfr_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_sfr[context->scratch1](context, target_cycle);
}
static void bit1_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_bit1[context->scratch1](context, target_cycle);
}
static void bit2_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_bit2[context->scratch1](context, target_cycle);
}
static void muldiv_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_muldiv[context->scratch1](context, target_cycle);
}
static void base_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_base[context->scratch1](context, target_cycle);
}
static void sfrbit_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_sfrbit[context->scratch1](context, target_cycle);
}
static void spmov_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_spmov[context->scratch1](context, target_cycle);
}
static void indexed_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_indexed[context->scratch1](context, target_cycle);
}
static void movw_sfrp_immed(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 == 252) {
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->sp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->sp = context->scratch1 | context->sp;
	} else {
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	offset = 1 + offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void movw_sadrp_word(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
	offset = 1 + offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void adjba(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint8_t diff;
	uint8_t tmp;
	uint8_t low;
	low = context->main[1] & 15;
	tmp = context->chflags & 8;
	if (tmp) {
	diff = 6;
	} else {
	if (low >= 10) {
	diff = 6;
	} else {
	diff = 0;
	}
	}
	tmp = context->chflags & 128;
	if (tmp) {
	diff = 96 | diff;
	context->chflags |= 128;
	} else {
	if (context->main[1] >= 154) {
	diff = 96 | diff;
	context->chflags |= 128;
	} else {
	context->chflags &= ~128;
	}
	}
	gen_tmp16__ = diff + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((diff ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
}
static void adjbs(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint8_t diff;
	uint8_t tmp;
	uint8_t low;
	low = context->main[1] & 15;
	tmp = context->chflags & 8;
	if (tmp) {
	diff = 6;
	} else {
	if (low >= 10) {
	diff = 6;
	} else {
	diff = 0;
	}
	}
	tmp = context->chflags & 128;
	if (tmp) {
	diff = 96 | diff;
	context->chflags |= 128;
	} else {
	if (context->main[1] >= 154) {
	diff = 96 | diff;
	context->chflags |= 128;
	} else {
	context->chflags &= ~128;
	}
	}
	gen_tmp16__ = context->main[1] - diff;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ diff ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
}
static void mov_a_sfr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->main[1] = context->scratch1;
}
static void movw_ax_sfr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 == 252) {
	context->main[0] = context->sp;
	context->main[1] = context->sp >> 8;
	} else {
	offset = context->scratch1;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->main[0] = context->scratch1;
	offset = 1 + offset;
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	context->main[1] = context->scratch1;
	}
}
static void mov_sfr_a(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1;
	context->scratch2 = context->scratch2 + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
}
static void movw_sfr_ax(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->scratch1 == 252) {
	context->sp = context->main[1] << 8;
	context->sp = context->main[0] | context->sp;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->main[0];
	upd78k2_write_8(context);
	offset = 1 + offset;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void br_rel(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	context->cycles += context->opts->gen.clock_divider * 6;
}
static void regind_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_regind[context->scratch1](context, target_cycle);
}
static void movw_saddr_ax(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->main[0];
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->main[0];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->main[0];
	upd78k2_write_8(context);
	}
	offset = 1 + offset;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->main[1];
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void movw_ax_saddr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->main[0] = context->scratch1;
	offset = 1 + offset;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void alu_ax_saddr_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint32_t gen_tmp32__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint8_t offset;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	offset = 1 + offset;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = context->scratch1 << 16;
	context->scratch1 = tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = context->scratch1 + aluop16_ax_tmp;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ aluop16_ax_tmp ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void alu_ax_saddr_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint8_t offset;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	offset = 1 + offset;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = context->scratch1 << 16;
	context->scratch1 = tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = aluop16_ax_tmp - context->scratch1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((aluop16_ax_tmp ^ context->scratch1 ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void alu_ax_saddr_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint8_t offset;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	offset = 1 + offset;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = context->scratch1 << 16;
	context->scratch1 = tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = aluop16_ax_tmp - context->scratch1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((aluop16_ax_tmp ^ context->scratch1 ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void mov_a_saddr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void mov_saddr_a(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1;
	if (context->scratch2 >= 32) {
	iram_write_normal_iram = 1;
	if (context->scratch2 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch2 >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch2 >= 240) {
	if (context->scratch2 >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch2 >= 232) {
	if (context->scratch2 >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch2 >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[context->scratch2] = context->main[1];
	} else {
	iram_write_regnum = context->scratch2 & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = context->scratch2 + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_mov_reg[context->scratch1](context, target_cycle);
}
static void xch_reg_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_xch_reg[context->scratch1](context, target_cycle);
}
static void inc_saddr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t gen_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	gen_tmp8__ = (context->scratch1 & 255) + (1 & 255);
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->scratch1 = (context->scratch1 & ~255) | (gen_tmp8__ & 255);
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void dec_saddr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t gen_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	gen_tmp8__ = (context->scratch1 & 255) - (1 & 255);
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->scratch1 = (context->scratch1 & ~255) | (gen_tmp8__ & 255);
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void call_long(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	address = context->scratch1;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void push_sfr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->scratch1;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov_sfr_immed(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (offset == 254) {
	context->psw = context->scratch1;
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
	upd78k2_sync_cycle(context, target_cycle);
	} else {
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void br_abs(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	context->pc = context->scratch1;
	context->cycles += context->opts->gen.clock_divider * 4;
}
static void alu_ax_immed_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint32_t gen_tmp32__;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = context->scratch1 + aluop16_ax_tmp;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ aluop16_ax_tmp ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void alu_ax_immed_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = aluop16_ax_tmp - context->scratch1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((aluop16_ax_tmp ^ context->scratch1 ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void alu_ax_immed_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint8_t upd78k2_op_fetch_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t aluop16_ax_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	upd78k2_op_fetch_word_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch1 = context->scratch1 << 8;
	context->scratch1 = upd78k2_op_fetch_word_tmp | context->scratch1;
	aluop16_ax_tmp = context->main[1] << 8;
	aluop16_ax_tmp = context->main[0] | aluop16_ax_tmp;
	{
	gen_tmp32__ = aluop16_ax_tmp - context->scratch1;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((aluop16_ax_tmp ^ context->scratch1 ^ gen_tmp32__) >> 9U & 8U);
	aluop16_ax_tmp = gen_tmp32__;
	}
	context->main[0] = aluop16_ax_tmp;
	context->main[1] = aluop16_ax_tmp >> 8;
}
static void shr_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_shr[context->scratch1](context, target_cycle);
}
static void shl_prefix(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_shl[context->scratch1](context, target_cycle);
}
static void dbnz_r_R_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t reg;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[2] = context->main[2] - 1;
	if (context->main[2]) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void dbnz_r_R_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t reg;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[3] = context->main[3] - 1;
	if (context->main[3]) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void pop_rp_P_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t rp;
	uint16_t word;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	word = context->scratch1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->scratch1 = context->scratch1 << 8;
	word = context->scratch1 | word;
	context->main[0] = word;
	context->main[1] = word >> 8;
}
static void pop_rp_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t rp;
	uint16_t word;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	word = context->scratch1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->scratch1 = context->scratch1 << 8;
	word = context->scratch1 | word;
	context->main[2] = word;
	context->main[3] = word >> 8;
}
static void pop_rp_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t rp;
	uint16_t word;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	word = context->scratch1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->scratch1 = context->scratch1 << 8;
	word = context->scratch1 | word;
	context->main[4] = word;
	context->main[5] = word >> 8;
}
static void pop_rp_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t rp;
	uint16_t word;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	word = context->scratch1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->scratch1 = context->scratch1 << 8;
	word = context->scratch1 | word;
	context->main[6] = word;
	context->main[7] = word >> 8;
}
static void mov_saddr_saddr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t src;
	uint8_t dstoff;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dstoff = context->scratch1;
	if (dstoff >= 32) {
	iram_write_normal_iram = 1;
	if (dstoff >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dstoff >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dstoff >= 240) {
	if (dstoff >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dstoff >= 232) {
	if (dstoff >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dstoff >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dstoff] = src;
	} else {
	iram_write_regnum = dstoff & 8;
	context->main[iram_write_regnum] = src;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dstoff + 65280;
	context->scratch1 = src;
	upd78k2_write_8(context);
	}
}
static void xch_saddr_saddr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dstoff;
	uint8_t srcoff;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	srcoff = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dstoff = context->scratch1;
	if (dstoff >= 32) {
	iram_read_normal_iram = 1;
	if (dstoff >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dstoff >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dstoff >= 240) {
	if (dstoff >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dstoff >= 232) {
	if (dstoff >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dstoff >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dstoff];
	} else {
	context->scratch1 = dstoff & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dstoff + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (srcoff >= 32) {
	iram_read_normal_iram = 1;
	if (srcoff >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (srcoff >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (srcoff >= 240) {
	if (srcoff >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (srcoff >= 232) {
	if (srcoff >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (srcoff >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[srcoff];
	} else {
	context->scratch1 = srcoff & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = srcoff + 65280;
	upd78k2_read_8(context);
	}
	if (dstoff >= 32) {
	iram_write_normal_iram = 1;
	if (dstoff >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dstoff >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dstoff >= 240) {
	if (dstoff >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dstoff >= 232) {
	if (dstoff >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dstoff >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dstoff] = context->scratch1;
	} else {
	iram_write_regnum = dstoff & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dstoff + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
	if (srcoff >= 32) {
	iram_write_normal_iram = 1;
	if (srcoff >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (srcoff >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (srcoff >= 240) {
	if (srcoff >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (srcoff >= 232) {
	if (srcoff >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (srcoff >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[srcoff] = tmp;
	} else {
	iram_write_regnum = srcoff & 8;
	context->main[iram_write_regnum] = tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = srcoff + 65280;
	context->scratch1 = tmp;
	upd78k2_write_8(context);
	}
}
static void mov_saddr_immed(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void push_rp_P_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t rp;
	uint16_t word;
	word = context->main[1] << 8;
	word = context->main[0] | word;
	push_word_tmp = word >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = word;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = word;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = word;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = word;
	upd78k2_write_8(context);
	}
}
static void push_rp_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t rp;
	uint16_t word;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	word = context->main[3] << 8;
	word = context->main[2] | word;
	push_word_tmp = word >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = word;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = word;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = word;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = word;
	upd78k2_write_8(context);
	}
}
static void push_rp_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t rp;
	uint16_t word;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	word = context->main[5] << 8;
	word = context->main[4] | word;
	push_word_tmp = word >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = word;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = word;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = word;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = word;
	upd78k2_write_8(context);
	}
}
static void push_rp_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t rp;
	uint16_t word;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	word = context->main[7] << 8;
	word = context->main[6] | word;
	push_word_tmp = word >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = word;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = word;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = word;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = word;
	upd78k2_write_8(context);
	}
}
static void clr1_cy(upd78k2_context *context, uint32_t target_cycle)
{
	context->chflags &= ~128;
}
static void set1_cy(upd78k2_context *context, uint32_t target_cycle)
{
	context->chflags |= 128;
}
static void not1_cy(upd78k2_context *context, uint32_t target_cycle)
{
	context->chflags = 128 ^ context->chflags;
}
static void pop_sfr(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
}
static void incw_rp_P_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[1] << 8;
	rp = context->main[0] | rp;
	gen_tmp16__ = 1 + rp;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ rp ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[0] = rp;
	context->main[1] = rp >> 8;
}
static void incw_rp_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[3] << 8;
	rp = context->main[2] | rp;
	gen_tmp16__ = 1 + rp;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ rp ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[2] = rp;
	context->main[3] = rp >> 8;
}
static void incw_rp_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[5] << 8;
	rp = context->main[4] | rp;
	gen_tmp16__ = 1 + rp;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ rp ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[4] = rp;
	context->main[5] = rp >> 8;
}
static void incw_rp_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[7] << 8;
	rp = context->main[6] | rp;
	gen_tmp16__ = 1 + rp;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ rp ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[6] = rp;
	context->main[7] = rp >> 8;
}
static void di(upd78k2_context *context, uint32_t target_cycle)
{
	context->int_enable = 0;
	upd78k2_sync_cycle(context, target_cycle);
}
static void ei(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	context->int_enable = 1;
	upd78k2_sync_cycle(context, target_cycle);
	if (context->cycles >= context->int_cycle) {
	context->int_cycle = context->cycles + 1;
	}
}
static void decw_rp_P_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[1] << 8;
	rp = context->main[0] | rp;
	gen_tmp16__ = rp - 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((rp ^ 1 ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[0] = rp;
	context->main[1] = rp >> 8;
}
static void decw_rp_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[3] << 8;
	rp = context->main[2] | rp;
	gen_tmp16__ = rp - 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((rp ^ 1 ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[2] = rp;
	context->main[3] = rp >> 8;
}
static void decw_rp_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[5] << 8;
	rp = context->main[4] | rp;
	gen_tmp16__ = rp - 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((rp ^ 1 ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[4] = rp;
	context->main[5] = rp >> 8;
}
static void decw_rp_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint16_t rp;
	uint8_t reg;
	rp = context->main[7] << 8;
	rp = context->main[6] | rp;
	gen_tmp16__ = rp - 1;
	context->zflag = gen_tmp16__ == 0;
	context->chflags = (context->chflags & ~8U) | ((rp ^ 1 ^ gen_tmp16__) >> 9U & 8U);
	rp = gen_tmp16__;
	context->main[6] = rp;
	context->main[7] = rp >> 8;
}
static void mov_reg_indirect_a_short_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_short_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_short_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_short_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	calc_addr_regind_tmp = context->scratch2 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_short_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[5] << 8;
	context->scratch2 = context->main[4] | context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void mov_reg_indirect_a_short_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_write_full_address;
	uint8_t mem_write_meg_enable;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch2 = context->main[7] << 8;
	context->scratch2 = context->main[6] | context->scratch2;
	}
	mem_write_meg_enable = context->mm & 64;
	if (mem_write_meg_enable) {
	mem_write_full_address = context->port_mode[6] & 15;
	mem_write_full_address = mem_write_full_address << 16;
	mem_write_full_address = context->scratch2 | mem_write_full_address;
	} else {
	mem_write_full_address = context->scratch2;
	}
	if (mem_write_full_address >= 65024) {
	if (mem_write_full_address >= 65280) {
	mem_write_no_exp_offset = mem_write_full_address;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = mem_write_full_address;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->main[1];
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->main[1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = mem_write_full_address;
	context->scratch1 = context->main[1];
	upd78k2_write_8(context);
	}
}
static void ret(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->pc = context->scratch1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->scratch1 = context->scratch1 << 8;
	context->pc = context->scratch1 | context->pc;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void reti(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->pc = context->scratch1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->scratch1 = context->scratch1 << 8;
	context->pc = context->scratch1 | context->pc;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_read_no_exp_offset = context->sp;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->sp;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->sp;
	upd78k2_read_8(context);
	}
	context->sp = 1 + context->sp;
	context->psw = context->scratch1;
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
	upd78k2_sync_cycle(context, target_cycle);
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->cycles += context->opts->gen.clock_divider * 18;
	context->int_enable = (context->psw & 128) != 0;
	context->zflag = (context->psw & 64) != 0;
	context->int_priority_flag = (context->psw & 2) != 0;
	context->rbs = 0;
	context->rbs |= context->psw >> 4 & 2;
	context->rbs |= context->psw >> 3 & 1;
	context->chflags = 0;
	context->chflags |= context->psw >> 1 & 8;
	context->chflags |= context->psw << 7 & 128;
}
static void mov_a_reg_indirect_short_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void mov_a_reg_indirect_short_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 + 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void mov_a_reg_indirect_short_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[4] = calc_addr_regind_tmp;
	context->main[5] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void mov_a_reg_indirect_short_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	calc_addr_regind_tmp = context->scratch1 - 1;
	context->main[6] = calc_addr_regind_tmp;
	context->main[7] = calc_addr_regind_tmp >> 8;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void mov_a_reg_indirect_short_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[5] << 8;
	context->scratch1 = context->main[4] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void mov_a_reg_indirect_short_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t calc_addr_regind_tmp;
	uint32_t mem_read_full_address;
	uint8_t mem_read_meg_enable;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	{
	context->scratch1 = context->main[7] << 8;
	context->scratch1 = context->main[6] | context->scratch1;
	}
	mem_read_meg_enable = context->mm & 64;
	if (mem_read_meg_enable) {
	mem_read_full_address = context->port_mode[6] & 15;
	mem_read_full_address = mem_read_full_address << 16;
	mem_read_full_address = context->scratch1 | mem_read_full_address;
	} else {
	mem_read_full_address = context->scratch1;
	}
	if (mem_read_full_address >= 65024) {
	if (mem_read_full_address >= 65280) {
	mem_read_no_exp_offset = mem_read_full_address;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = mem_read_full_address;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = mem_read_full_address;
	upd78k2_read_8(context);
	}
	context->main[1] = context->scratch1;
}
static void movw_rp_immed_P_00(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[0] = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[1] = context->scratch1;
}
static void movw_rp_immed_P_01(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[2] = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[3] = context->scratch1;
}
static void movw_rp_immed_P_10(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[4] = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[5] = context->scratch1;
}
static void movw_rp_immed_P_11(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[6] = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[7] = context->scratch1;
}
static void alu_saddr_immed_P_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint64_t gen_tmp64__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	uint8_t immed;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp64__ = ((uint64_t)immed) + ((uint64_t)context->scratch1);
	context->zflag = (gen_tmp64__ & 4294967295) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp64__ >> 25U & 128U);
	context->chflags = (context->chflags & ~8U) | ((immed ^ context->scratch1 ^ gen_tmp64__) >> 25U & 8U);
	context->scratch1 = gen_tmp64__;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_immed_P_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	uint8_t immed;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp64__ = ((uint64_t)immed) + ((uint64_t)context->scratch1) + ((context->chflags & 1 << 7) ? ((uint64_t)1) : ((uint64_t)0));
	context->zflag = (gen_tmp64__ & 4294967295) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp64__ >> 25U & 128U);
	context->chflags = (context->chflags & ~8U) | ((immed ^ context->scratch1 ^ gen_tmp64__) >> 25U & 8U);
	context->scratch1 = gen_tmp64__;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_immed_P_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	uint8_t immed;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp64__ = ((uint64_t)context->scratch1) - ((uint64_t)immed);
	context->zflag = (gen_tmp64__ & 4294967295) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp64__ >> 25U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ immed ^ gen_tmp64__) >> 25U & 8U);
	context->scratch1 = gen_tmp64__;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_immed_P_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint64_t gen_tmp64__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	uint8_t immed;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp64__ = ((uint64_t)context->scratch1) - ((uint64_t)immed) - ((context->chflags & 1 << 7) ? ((uint64_t)1) : ((uint64_t)0));
	context->zflag = (gen_tmp64__ & 4294967295) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp64__ >> 25U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ immed ^ gen_tmp64__) >> 25U & 8U);
	context->scratch1 = gen_tmp64__;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_immed_P_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	uint8_t immed;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	context->scratch1 = immed & context->scratch1;
	context->zflag = context->scratch1 == 0;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_immed_P_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	uint8_t immed;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	context->scratch1 = immed ^ context->scratch1;
	context->zflag = context->scratch1 == 0;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_immed_P_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t offset;
	uint8_t immed;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	context->scratch1 = immed | context->scratch1;
	context->zflag = context->scratch1 == 0;
	}
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_immed_P_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint64_t cmp_tmp64__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t offset;
	uint8_t immed;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	immed = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp64__ = ((uint64_t)context->scratch1) - ((uint64_t)((immed) & 4294967295));
	context->zflag = (cmp_tmp64__ & 4294967295) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp64__ >> 25U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ immed ^ cmp_tmp64__) >> 25U & 8U);
	}
}
static void bt_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 1;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 2;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 4;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 8;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 16;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 32;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 64;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void bt_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t mask;
	uint8_t tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	mask = tmp & 128;
	if (mask) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	}
}
static void alu_saddr_saddr_P_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	gen_tmp16__ = src_tmp + dst_tmp;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((src_tmp ^ dst_tmp ^ gen_tmp16__) >> 1U & 8U);
	dst_tmp = gen_tmp16__;
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_saddr_P_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	gen_tmp16__ = src_tmp + dst_tmp + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((src_tmp ^ dst_tmp ^ gen_tmp16__) >> 1U & 8U);
	dst_tmp = gen_tmp16__;
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_saddr_P_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	gen_tmp16__ = dst_tmp - src_tmp;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((dst_tmp ^ src_tmp ^ gen_tmp16__) >> 1U & 8U);
	dst_tmp = gen_tmp16__;
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_saddr_P_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	gen_tmp16__ = dst_tmp - src_tmp - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((dst_tmp ^ src_tmp ^ gen_tmp16__) >> 1U & 8U);
	dst_tmp = gen_tmp16__;
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_saddr_P_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	dst_tmp = src_tmp & dst_tmp;
	context->zflag = dst_tmp == 0;
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_saddr_P_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	dst_tmp = src_tmp ^ dst_tmp;
	context->zflag = dst_tmp == 0;
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_saddr_P_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	dst_tmp = src_tmp | dst_tmp;
	context->zflag = dst_tmp == 0;
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void alu_saddr_saddr_P_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t dst_offset;
	uint8_t src_tmp;
	uint8_t dst_tmp;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	src_tmp = context->scratch1;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	dst_offset = context->scratch1;
	if (dst_offset >= 32) {
	iram_read_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[dst_offset];
	} else {
	context->scratch1 = dst_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = dst_offset + 65280;
	upd78k2_read_8(context);
	}
	dst_tmp = context->scratch1;
	{
	cmp_tmp16__ = dst_tmp - src_tmp;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((dst_tmp ^ src_tmp ^ cmp_tmp16__) >> 1U & 8U);
	}
	if (dst_offset >= 32) {
	iram_write_normal_iram = 1;
	if (dst_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (dst_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (dst_offset >= 240) {
	if (dst_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (dst_offset >= 232) {
	if (dst_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (dst_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[dst_offset] = dst_tmp;
	} else {
	iram_write_regnum = dst_offset & 8;
	context->main[iram_write_regnum] = dst_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = dst_offset + 65280;
	context->scratch1 = dst_tmp;
	upd78k2_write_8(context);
	}
}
static void bcc_F_0_S_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t flag;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	flag = context->zflag;
	if (flag == 0) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	context->cycles += context->opts->gen.clock_divider * 6;
	}
}
static void bcc_F_0_S_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t flag;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	flag = context->zflag;
	if (flag == 1) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	context->cycles += context->opts->gen.clock_divider * 6;
	}
}
static void bcc_F_1_S_0(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t flag;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	flag = context->chflags >> 7;
	if (flag == 0) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	context->cycles += context->opts->gen.clock_divider * 6;
	}
}
static void bcc_F_1_S_1(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t flag;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	flag = context->chflags >> 7;
	if (flag == 1) {
	context->scratch1 = (context->scratch1 & ~65535) | ((context->scratch1 & 255) & 128 ? (context->scratch1 & 255) | 65280 : (context->scratch1 & 255));
	context->pc = context->scratch1 + context->pc;
	context->cycles += context->opts->gen.clock_divider * 6;
	}
}
static void alu_r_r_P_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint32_t gen_tmp32__;
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	{
	gen_tmp32__ = tmp_src + tmp_dst;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((tmp_src ^ tmp_dst ^ gen_tmp32__) >> 9U & 8U);
	tmp_dst = gen_tmp32__;
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	gen_tmp16__ = context->main[context->scratch1] + context->main[context->scratch2];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[context->scratch1] ^ context->main[context->scratch2] ^ gen_tmp16__) >> 1U & 8U);
	context->main[context->scratch2] = gen_tmp16__;
	}
	}
	}
}
static void alu_r_r_P_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	gen_tmp16__ = context->main[context->scratch1] + context->main[context->scratch2] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[context->scratch1] ^ context->main[context->scratch2] ^ gen_tmp16__) >> 1U & 8U);
	context->main[context->scratch2] = gen_tmp16__;
	}
	}
	}
}
static void alu_r_r_P_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t gen_tmp32__;
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	{
	gen_tmp32__ = tmp_dst - tmp_src;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((tmp_dst ^ tmp_src ^ gen_tmp32__) >> 9U & 8U);
	tmp_dst = gen_tmp32__;
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	gen_tmp16__ = context->main[context->scratch2] - context->main[context->scratch1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[context->scratch2] ^ context->main[context->scratch1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[context->scratch2] = gen_tmp16__;
	}
	}
	}
}
static void alu_r_r_P_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	gen_tmp16__ = context->main[context->scratch2] - context->main[context->scratch1] - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[context->scratch2] ^ context->main[context->scratch1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[context->scratch2] = gen_tmp16__;
	}
	}
	}
}
static void alu_r_r_P_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	context->main[context->scratch2] = context->main[context->scratch1] & context->main[context->scratch2];
	context->zflag = (context->main[context->scratch2] & 255) == 0;
	}
	}
	}
}
static void alu_r_r_P_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	context->main[context->scratch2] = context->main[context->scratch1] ^ context->main[context->scratch2];
	context->zflag = (context->main[context->scratch2] & 255) == 0;
	}
	}
	}
}
static void alu_r_r_P_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	context->main[context->scratch2] = context->main[context->scratch1] | context->main[context->scratch2];
	context->zflag = (context->main[context->scratch2] & 255) == 0;
	}
	}
	}
}
static void alu_r_r_P_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint32_t gen_tmp32__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint16_t tmp_src;
	uint16_t tmp_dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->scratch2 = context->scratch1 >> 4;
	if (context->scratch2 >= 7) {
	} else {
	context->scratch1 = 15 & context->scratch1;
	if (context->scratch1 >= 7) {
	context->scratch1 = 7 & context->scratch1;
	tmp_dst = context->main[1] << 8;
	tmp_dst = context->main[0] | tmp_dst;
	switch(context->scratch1)
	{
	case 0U: {
	tmp_src = context->main[1] << 8;
	tmp_src = context->main[0] | tmp_src;
	break;
	}
	case 2U: {
	tmp_src = context->main[3] << 8;
	tmp_src = context->main[2] | tmp_src;
	break;
	}
	case 4U: {
	tmp_src = context->main[5] << 8;
	tmp_src = context->main[4] | tmp_src;
	break;
	}
	case 6U: {
	tmp_src = context->main[7] << 8;
	tmp_src = context->main[6] | tmp_src;
	break;
	}
	}
	{
	gen_tmp32__ = tmp_dst - tmp_src;
	context->zflag = (gen_tmp32__ & 65535) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp32__ >> 9U & 128U);
	context->chflags = (context->chflags & ~8U) | ((tmp_dst ^ tmp_src ^ gen_tmp32__) >> 9U & 8U);
	tmp_dst = gen_tmp32__;
	}
	context->main[0] = tmp_dst;
	context->main[1] = tmp_dst >> 8;
	} else {
	context->cycles += context->opts->gen.clock_divider * 2;
	{
	cmp_tmp16__ = context->main[context->scratch2] - context->main[context->scratch1];
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[context->scratch2] ^ context->main[context->scratch1] ^ cmp_tmp16__) >> 1U & 8U);
	}
	}
	}
}
static void call_short_A_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 2048;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void call_short_A_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 2304;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void call_short_A_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 2560;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void call_short_A_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 2816;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void call_short_A_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 3072;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void call_short_A_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 3328;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void call_short_A_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 3584;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void call_short_A_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	address = context->scratch1 | 3840;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 12;
}
static void alu_a_saddr_P_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_a_saddr_P_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_a_saddr_P_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_a_saddr_P_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_a_saddr_P_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_a_saddr_P_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_a_saddr_P_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_a_saddr_P_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	if (context->scratch1 >= 32) {
	iram_read_normal_iram = 1;
	if (context->scratch1 >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (context->scratch1 >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (context->scratch1 >= 240) {
	if (context->scratch1 >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (context->scratch1 >= 232) {
	if (context->scratch1 >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (context->scratch1 >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[context->scratch1];
	} else {
	context->scratch1 = context->scratch1 & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = context->scratch1 + 65280;
	upd78k2_read_8(context);
	}
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void clr1_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -2 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void clr1_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -3 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void clr1_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -5 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void clr1_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -9 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void clr1_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -17 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void clr1_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -33 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void clr1_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -65 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void clr1_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = -129 & context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void alu_immed_P_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	gen_tmp16__ = context->scratch1 + context->main[1];
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_immed_P_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	gen_tmp16__ = context->scratch1 + context->main[1] + ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->scratch1 ^ context->main[1] ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_immed_P_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	gen_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_immed_P_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t gen_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	gen_tmp16__ = context->main[1] - context->scratch1 - ((context->chflags & 1 << 7) ? 1 : 0);
	context->zflag = (gen_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (gen_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ gen_tmp16__) >> 1U & 8U);
	context->main[1] = gen_tmp16__;
	}
}
static void alu_immed_P_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	context->main[1] = context->scratch1 & context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_immed_P_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	context->main[1] = context->scratch1 ^ context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_immed_P_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	context->main[1] = context->scratch1 | context->main[1];
	context->zflag = (context->main[1] & 255) == 0;
	}
}
static void alu_immed_P_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t cmp_tmp16__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	{
	cmp_tmp16__ = context->main[1] - context->scratch1;
	context->zflag = (cmp_tmp16__ & 255) == 0;
	context->chflags = (context->chflags & ~128U) | (cmp_tmp16__ >> 1U & 128U);
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ context->scratch1 ^ cmp_tmp16__) >> 1U & 8U);
	}
}
static void set1_saddr_B_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 1 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void set1_saddr_B_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 2 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void set1_saddr_B_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 4 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void set1_saddr_B_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 8 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void set1_saddr_B_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 16 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void set1_saddr_B_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 32 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void set1_saddr_B_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 64 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void set1_saddr_B_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t mask;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	offset = context->scratch1;
	if (offset >= 32) {
	iram_read_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[offset];
	} else {
	context->scratch1 = offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch1 = offset + 65280;
	upd78k2_read_8(context);
	}
	context->scratch1 = 128 | context->scratch1;
	if (offset >= 32) {
	iram_write_normal_iram = 1;
	if (offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (offset >= 240) {
	if (offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (offset >= 232) {
	if (offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[offset] = context->scratch1;
	} else {
	iram_write_regnum = offset & 8;
	context->main[iram_write_regnum] = context->scratch1;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	} else {
	context->scratch2 = offset + 65280;
	context->scratch1 = context->scratch1;
	upd78k2_write_8(context);
	}
}
static void mov_r_immed_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[0] = context->scratch1;
}
static void mov_r_immed_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[1] = context->scratch1;
}
static void mov_r_immed_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[2] = context->scratch1;
}
static void mov_r_immed_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[3] = context->scratch1;
}
static void mov_r_immed_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[4] = context->scratch1;
}
static void mov_r_immed_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[5] = context->scratch1;
}
static void mov_r_immed_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[6] = context->scratch1;
}
static void mov_r_immed_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint8_t dst;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	context->main[7] = context->scratch1;
}
static void inc_r_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[0];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[0] ^ gen_tmp8__) >> 1U & 8U);
	context->main[0] = gen_tmp8__;
}
static void inc_r_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[1];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[1] ^ gen_tmp8__) >> 1U & 8U);
	context->main[1] = gen_tmp8__;
}
static void inc_r_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[2];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[2] ^ gen_tmp8__) >> 1U & 8U);
	context->main[2] = gen_tmp8__;
}
static void inc_r_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[3];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[3] ^ gen_tmp8__) >> 1U & 8U);
	context->main[3] = gen_tmp8__;
}
static void inc_r_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[4];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[4] ^ gen_tmp8__) >> 1U & 8U);
	context->main[4] = gen_tmp8__;
}
static void inc_r_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[5];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[5] ^ gen_tmp8__) >> 1U & 8U);
	context->main[5] = gen_tmp8__;
}
static void inc_r_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[6];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[6] ^ gen_tmp8__) >> 1U & 8U);
	context->main[6] = gen_tmp8__;
}
static void inc_r_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = 1 + context->main[7];
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((1 ^ context->main[7] ^ gen_tmp8__) >> 1U & 8U);
	context->main[7] = gen_tmp8__;
}
static void dec_r_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[0] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[0] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[0] = gen_tmp8__;
}
static void dec_r_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[1] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[1] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[1] = gen_tmp8__;
}
static void dec_r_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[2] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[2] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[2] = gen_tmp8__;
}
static void dec_r_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[3] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[3] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[3] = gen_tmp8__;
}
static void dec_r_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[4] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[4] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[4] = gen_tmp8__;
}
static void dec_r_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[5] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[5] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[5] = gen_tmp8__;
}
static void dec_r_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[6] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[6] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[6] = gen_tmp8__;
}
static void dec_r_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	context->cycles += context->opts->gen.clock_divider * 2;
	gen_tmp8__ = context->main[7] - 1;
	context->zflag = gen_tmp8__ == 0;
	context->chflags = (context->chflags & ~8U) | ((context->main[7] ^ 1 ^ gen_tmp8__) >> 1U & 8U);
	context->main[7] = gen_tmp8__;
}
static void mov_a_r_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[0];
}
static void mov_a_r_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[1];
}
static void mov_a_r_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[2];
}
static void mov_a_r_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[3];
}
static void mov_a_r_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[4];
}
static void mov_a_r_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[5];
}
static void mov_a_r_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[6];
}
static void mov_a_r_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	context->main[1] = context->main[7];
}
static void xch_a_r_R_000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[0];
	context->main[0] = gen_tmp8__;
}
static void xch_a_r_R_001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[1];
	context->main[1] = gen_tmp8__;
}
static void xch_a_r_R_010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[2];
	context->main[2] = gen_tmp8__;
}
static void xch_a_r_R_011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[3];
	context->main[3] = gen_tmp8__;
}
static void xch_a_r_R_100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[4];
	context->main[4] = gen_tmp8__;
}
static void xch_a_r_R_101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[5];
	context->main[5] = gen_tmp8__;
}
static void xch_a_r_R_110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[6];
	context->main[6] = gen_tmp8__;
}
static void xch_a_r_R_111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t gen_tmp8__;
	gen_tmp8__ = context->main[1];
	context->main[1] = context->main[7];
	context->main[7] = gen_tmp8__;
}
static void call_table_T_00000(upd78k2_context *context, uint32_t target_cycle)
{
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	context->scratch1 = 64;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 65;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_00001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 66;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 67;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_00010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 68;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 69;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_00011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 70;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 71;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_00100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 72;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 73;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_00101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 74;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 75;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_00110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 76;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 77;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_00111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 78;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 79;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 80;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 81;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 82;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 83;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 84;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 85;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 86;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 87;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 88;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 89;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 90;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 91;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 92;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 93;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_01111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 94;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 95;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 96;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 97;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 98;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 99;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 100;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 101;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 102;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 103;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 104;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 105;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 106;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 107;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 108;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 109;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_10111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 110;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 111;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11000(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 112;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 113;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11001(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 114;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 115;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11010(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 116;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 117;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11011(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 118;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 119;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11100(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 120;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 121;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11101(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 122;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 123;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11110(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 124;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 125;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void call_table_T_11111(upd78k2_context *context, uint32_t target_cycle)
{
	uint8_t mem_read_no_exp_offset;
	uint8_t push_word_tmp;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint16_t address;
	uint8_t offset;
	uint32_t cmp_tmp32__;
	uint8_t cmp_tmp8__;
	context->scratch1 = 126;
	upd78k2_read_8(context);
	address = context->scratch1;
	context->scratch1 = 127;
	upd78k2_read_8(context);
	context->scratch1 = context->scratch1 << 8;
	address = context->scratch1 | address;
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->pc = address;
	context->cycles += context->opts->gen.clock_divider * 18;
}
static void unimplemented(upd78k2_context *context, uint32_t target_cycle)
{
	fatal_error("Unimplemented instruction: %X, pc=%X\n", context->scratch1, context->pc - 0);
}

static impl_fun impl_sfr[256] = {
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_base_prefix,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_indexed_prefix,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_regind_prefix,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_ax_sfr_P_01,
	alu_ax_sfr_P_10,
	alu_ax_sfr_P_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_bit1[256] = {
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	bf_psw_B_000,
	bf_psw_B_001,
	bf_psw_B_010,
	bf_psw_B_011,
	bf_psw_B_100,
	bf_psw_B_101,
	bf_psw_B_110,
	bf_psw_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	bt_psw_B_000,
	bt_psw_B_001,
	bt_psw_B_010,
	bt_psw_B_011,
	bt_psw_B_100,
	bt_psw_B_101,
	bt_psw_B_110,
	bt_psw_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	btclr_psw_B_000,
	btclr_psw_B_001,
	btclr_psw_B_010,
	btclr_psw_B_011,
	btclr_psw_B_100,
	btclr_psw_B_101,
	btclr_psw_B_110,
	btclr_psw_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_bit2[256] = {
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	bf_r_B_000_R_0,
	bf_r_B_001_R_0,
	bf_r_B_010_R_0,
	bf_r_B_011_R_0,
	bf_r_B_100_R_0,
	bf_r_B_101_R_0,
	bf_r_B_110_R_0,
	bf_r_B_111_R_0,
	bf_r_B_000_R_1,
	bf_r_B_001_R_1,
	bf_r_B_010_R_1,
	bf_r_B_011_R_1,
	bf_r_B_100_R_1,
	bf_r_B_101_R_1,
	bf_r_B_110_R_1,
	bf_r_B_111_R_1,
	bt_r_B_000_R_0,
	bt_r_B_001_R_0,
	bt_r_B_010_R_0,
	bt_r_B_011_R_0,
	bt_r_B_100_R_0,
	bt_r_B_101_R_0,
	bt_r_B_110_R_0,
	bt_r_B_111_R_0,
	bt_r_B_000_R_1,
	bt_r_B_001_R_1,
	bt_r_B_010_R_1,
	bt_r_B_011_R_1,
	bt_r_B_100_R_1,
	bt_r_B_101_R_1,
	bt_r_B_110_R_1,
	bt_r_B_111_R_1,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	btclr_r_B_000_R_0,
	btclr_r_B_001_R_0,
	btclr_r_B_010_R_0,
	btclr_r_B_011_R_0,
	btclr_r_B_100_R_0,
	btclr_r_B_101_R_0,
	btclr_r_B_110_R_0,
	btclr_r_B_111_R_0,
	btclr_r_B_000_R_1,
	btclr_r_B_001_R_1,
	btclr_r_B_010_R_1,
	btclr_r_B_011_R_1,
	btclr_r_B_100_R_1,
	btclr_r_B_101_R_1,
	btclr_r_B_110_R_1,
	btclr_r_B_111_R_1,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_muldiv[256] = {
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mulu_R_000,
	mulu_R_001,
	mulu_R_010,
	mulu_R_011,
	mulu_R_100,
	mulu_R_101,
	mulu_R_110,
	mulu_R_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	divuw_R_000,
	divuw_R_001,
	divuw_R_010,
	divuw_R_011,
	divuw_R_100,
	divuw_R_101,
	divuw_R_110,
	divuw_R_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	br_rp_P_00,
	unimplemented,
	br_rp_P_01,
	unimplemented,
	br_rp_P_10,
	unimplemented,
	br_rp_P_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	call_rp_P_00,
	unimplemented,
	call_rp_P_01,
	unimplemented,
	call_rp_P_10,
	unimplemented,
	call_rp_P_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	sel_N_00,
	sel_N_01,
	sel_N_10,
	sel_N_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	incw_sp,
	decw_sp,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	movw_ax_mem_R_0,
	movw_ax_mem_R_1,
	unimplemented,
	unimplemented,
	movw_mem_ax_R_0,
	movw_mem_ax_R_1,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_base[256] = {
	mov_a_base_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_base_P_000_R_00,
	alu_base_P_001_R_00,
	alu_base_P_010_R_00,
	alu_base_P_011_R_00,
	alu_base_P_100_R_00,
	alu_base_P_101_R_00,
	alu_base_P_110_R_00,
	alu_base_P_111_R_00,
	mov_a_base_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_base_P_000_R_01,
	alu_base_P_001_R_01,
	alu_base_P_010_R_01,
	alu_base_P_011_R_01,
	alu_base_P_100_R_01,
	alu_base_P_101_R_01,
	alu_base_P_110_R_01,
	alu_base_P_111_R_01,
	mov_a_base_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_base_P_000_R_10,
	alu_base_P_001_R_10,
	alu_base_P_010_R_10,
	alu_base_P_011_R_10,
	alu_base_P_100_R_10,
	alu_base_P_101_R_10,
	alu_base_P_110_R_10,
	alu_base_P_111_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_base_a_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_base_a_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_base_a_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_sfrbit[256] = {
	mov1_cy_saddr_B_000,
	mov1_cy_saddr_B_001,
	mov1_cy_saddr_B_010,
	mov1_cy_saddr_B_011,
	mov1_cy_saddr_B_100,
	mov1_cy_saddr_B_101,
	mov1_cy_saddr_B_110,
	mov1_cy_saddr_B_111,
	mov1_cy_sfr_B_000,
	mov1_cy_sfr_B_001,
	mov1_cy_sfr_B_010,
	mov1_cy_sfr_B_011,
	mov1_cy_sfr_B_100,
	mov1_cy_sfr_B_101,
	mov1_cy_sfr_B_110,
	mov1_cy_sfr_B_111,
	mov1_saddr_cy_B_000,
	mov1_saddr_cy_B_001,
	mov1_saddr_cy_B_010,
	mov1_saddr_cy_B_011,
	mov1_saddr_cy_B_100,
	mov1_saddr_cy_B_101,
	mov1_saddr_cy_B_110,
	mov1_saddr_cy_B_111,
	mov1_sfr_cy_B_000,
	mov1_sfr_cy_B_001,
	mov1_sfr_cy_B_010,
	mov1_sfr_cy_B_011,
	mov1_sfr_cy_B_100,
	mov1_sfr_cy_B_101,
	mov1_sfr_cy_B_110,
	mov1_sfr_cy_B_111,
	and1_cy_saddr_B_000_I_0,
	and1_cy_saddr_B_001_I_0,
	and1_cy_saddr_B_010_I_0,
	and1_cy_saddr_B_011_I_0,
	and1_cy_saddr_B_100_I_0,
	and1_cy_saddr_B_101_I_0,
	and1_cy_saddr_B_110_I_0,
	and1_cy_saddr_B_111_I_0,
	and1_cy_sfr_B_000_I_0,
	and1_cy_sfr_B_001_I_0,
	and1_cy_sfr_B_010_I_0,
	and1_cy_sfr_B_011_I_0,
	and1_cy_sfr_B_100_I_0,
	and1_cy_sfr_B_101_I_0,
	and1_cy_sfr_B_110_I_0,
	and1_cy_sfr_B_111_I_0,
	and1_cy_saddr_B_000_I_1,
	and1_cy_saddr_B_001_I_1,
	and1_cy_saddr_B_010_I_1,
	and1_cy_saddr_B_011_I_1,
	and1_cy_saddr_B_100_I_1,
	and1_cy_saddr_B_101_I_1,
	and1_cy_saddr_B_110_I_1,
	and1_cy_saddr_B_111_I_1,
	and1_cy_sfr_B_000_I_1,
	and1_cy_sfr_B_001_I_1,
	and1_cy_sfr_B_010_I_1,
	and1_cy_sfr_B_011_I_1,
	and1_cy_sfr_B_100_I_1,
	and1_cy_sfr_B_101_I_1,
	and1_cy_sfr_B_110_I_1,
	and1_cy_sfr_B_111_I_1,
	or1_cy_saddr_B_000_I_0,
	or1_cy_saddr_B_001_I_0,
	or1_cy_saddr_B_010_I_0,
	or1_cy_saddr_B_011_I_0,
	or1_cy_saddr_B_100_I_0,
	or1_cy_saddr_B_101_I_0,
	or1_cy_saddr_B_110_I_0,
	or1_cy_saddr_B_111_I_0,
	or1_cy_sfr_B_000_I_0,
	or1_cy_sfr_B_001_I_0,
	or1_cy_sfr_B_010_I_0,
	or1_cy_sfr_B_011_I_0,
	or1_cy_sfr_B_100_I_0,
	or1_cy_sfr_B_101_I_0,
	or1_cy_sfr_B_110_I_0,
	or1_cy_sfr_B_111_I_0,
	or1_cy_saddr_B_000_I_1,
	or1_cy_saddr_B_001_I_1,
	or1_cy_saddr_B_010_I_1,
	or1_cy_saddr_B_011_I_1,
	or1_cy_saddr_B_100_I_1,
	or1_cy_saddr_B_101_I_1,
	or1_cy_saddr_B_110_I_1,
	or1_cy_saddr_B_111_I_1,
	or1_cy_sfr_B_000_I_1,
	or1_cy_sfr_B_001_I_1,
	or1_cy_sfr_B_010_I_1,
	or1_cy_sfr_B_011_I_1,
	or1_cy_sfr_B_100_I_1,
	or1_cy_sfr_B_101_I_1,
	or1_cy_sfr_B_110_I_1,
	or1_cy_sfr_B_111_I_1,
	xor1_cy_saddr_B_000,
	xor1_cy_saddr_B_001,
	xor1_cy_saddr_B_010,
	xor1_cy_saddr_B_011,
	xor1_cy_saddr_B_100,
	xor1_cy_saddr_B_101,
	xor1_cy_saddr_B_110,
	xor1_cy_saddr_B_111,
	xor1_cy_sfr_B_000,
	xor1_cy_sfr_B_001,
	xor1_cy_sfr_B_010,
	xor1_cy_sfr_B_011,
	xor1_cy_sfr_B_100,
	xor1_cy_sfr_B_101,
	xor1_cy_sfr_B_110,
	xor1_cy_sfr_B_111,
	not1_saddr_B_000,
	not1_saddr_B_001,
	not1_saddr_B_010,
	not1_saddr_B_011,
	not1_saddr_B_100,
	not1_saddr_B_101,
	not1_saddr_B_110,
	not1_saddr_B_111,
	not1_sfr_B_000,
	not1_sfr_B_001,
	not1_sfr_B_010,
	not1_sfr_B_011,
	not1_sfr_B_100,
	not1_sfr_B_101,
	not1_sfr_B_110,
	not1_sfr_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	set1_sfr_B_000,
	set1_sfr_B_001,
	set1_sfr_B_010,
	set1_sfr_B_011,
	set1_sfr_B_100,
	set1_sfr_B_101,
	set1_sfr_B_110,
	set1_sfr_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	clr1_sfr_B_000,
	clr1_sfr_B_001,
	clr1_sfr_B_010,
	clr1_sfr_B_011,
	clr1_sfr_B_100,
	clr1_sfr_B_101,
	clr1_sfr_B_110,
	clr1_sfr_B_111,
	bf_saddr_B_000,
	bf_saddr_B_001,
	bf_saddr_B_010,
	bf_saddr_B_011,
	bf_saddr_B_100,
	bf_saddr_B_101,
	bf_saddr_B_110,
	bf_saddr_B_111,
	bf_sfr_B_000,
	bf_sfr_B_001,
	bf_sfr_B_010,
	bf_sfr_B_011,
	bf_sfr_B_100,
	bf_sfr_B_101,
	bf_sfr_B_110,
	bf_sfr_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	bt_sfr_B_000,
	bt_sfr_B_001,
	bt_sfr_B_010,
	bt_sfr_B_011,
	bt_sfr_B_100,
	bt_sfr_B_101,
	bt_sfr_B_110,
	bt_sfr_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	btclr_saddr_B_000,
	btclr_saddr_B_001,
	btclr_saddr_B_010,
	btclr_saddr_B_011,
	btclr_saddr_B_100,
	btclr_saddr_B_101,
	btclr_saddr_B_110,
	btclr_saddr_B_111,
	btclr_sfr_B_000,
	btclr_sfr_B_001,
	btclr_sfr_B_010,
	btclr_sfr_B_011,
	btclr_sfr_B_100,
	btclr_sfr_B_101,
	btclr_sfr_B_110,
	btclr_sfr_B_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_spmov[256] = {
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_stbc_immed,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_a_abs,
	mov_abs_a,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_indexed[256] = {
	mov_a_indexed_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_indexed_P_000_R_00,
	alu_indexed_P_001_R_00,
	alu_indexed_P_010_R_00,
	alu_indexed_P_011_R_00,
	alu_indexed_P_100_R_00,
	alu_indexed_P_101_R_00,
	alu_indexed_P_110_R_00,
	alu_indexed_P_111_R_00,
	mov_a_indexed_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_indexed_P_000_R_01,
	alu_indexed_P_001_R_01,
	alu_indexed_P_010_R_01,
	alu_indexed_P_011_R_01,
	alu_indexed_P_100_R_01,
	alu_indexed_P_101_R_01,
	alu_indexed_P_110_R_01,
	alu_indexed_P_111_R_01,
	mov_a_indexed_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_indexed_P_000_R_10,
	alu_indexed_P_001_R_10,
	alu_indexed_P_010_R_10,
	alu_indexed_P_011_R_10,
	alu_indexed_P_100_R_10,
	alu_indexed_P_101_R_10,
	alu_indexed_P_110_R_10,
	alu_indexed_P_111_R_10,
	mov_a_indexed_R_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_indexed_P_000_R_11,
	alu_indexed_P_001_R_11,
	alu_indexed_P_010_R_11,
	alu_indexed_P_011_R_11,
	alu_indexed_P_100_R_11,
	alu_indexed_P_101_R_11,
	alu_indexed_P_110_R_11,
	alu_indexed_P_111_R_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_indexed_a_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_indexed_a_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_indexed_a_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_indexed_a_R_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_regind[256] = {
	mov_a_reg_indirect_R_000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_reg_indirect_P_000_R_000,
	alu_reg_indirect_P_001_R_000,
	alu_reg_indirect_P_010_R_000,
	alu_reg_indirect_P_011_R_000,
	alu_reg_indirect_P_100_R_000,
	alu_reg_indirect_P_101_R_000,
	alu_reg_indirect_P_110_R_000,
	alu_reg_indirect_P_111_R_000,
	mov_a_reg_indirect_R_001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_reg_indirect_P_000_R_001,
	alu_reg_indirect_P_001_R_001,
	alu_reg_indirect_P_010_R_001,
	alu_reg_indirect_P_011_R_001,
	alu_reg_indirect_P_100_R_001,
	alu_reg_indirect_P_101_R_001,
	alu_reg_indirect_P_110_R_001,
	alu_reg_indirect_P_111_R_001,
	mov_a_reg_indirect_R_010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_reg_indirect_P_000_R_010,
	alu_reg_indirect_P_001_R_010,
	alu_reg_indirect_P_010_R_010,
	alu_reg_indirect_P_011_R_010,
	alu_reg_indirect_P_100_R_010,
	alu_reg_indirect_P_101_R_010,
	alu_reg_indirect_P_110_R_010,
	alu_reg_indirect_P_111_R_010,
	mov_a_reg_indirect_R_011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_reg_indirect_P_000_R_011,
	alu_reg_indirect_P_001_R_011,
	alu_reg_indirect_P_010_R_011,
	alu_reg_indirect_P_011_R_011,
	alu_reg_indirect_P_100_R_011,
	alu_reg_indirect_P_101_R_011,
	alu_reg_indirect_P_110_R_011,
	alu_reg_indirect_P_111_R_011,
	mov_a_reg_indirect_R_100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_reg_indirect_P_000_R_100,
	alu_reg_indirect_P_001_R_100,
	alu_reg_indirect_P_010_R_100,
	alu_reg_indirect_P_011_R_100,
	alu_reg_indirect_P_100_R_100,
	alu_reg_indirect_P_101_R_100,
	alu_reg_indirect_P_110_R_100,
	alu_reg_indirect_P_111_R_100,
	mov_a_reg_indirect_R_101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_reg_indirect_P_000_R_101,
	alu_reg_indirect_P_001_R_101,
	alu_reg_indirect_P_010_R_101,
	alu_reg_indirect_P_011_R_101,
	alu_reg_indirect_P_100_R_101,
	alu_reg_indirect_P_101_R_101,
	alu_reg_indirect_P_110_R_101,
	alu_reg_indirect_P_111_R_101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_reg_indirect_a_R_000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_reg_indirect_a_R_001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_reg_indirect_a_R_010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_reg_indirect_a_R_011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_reg_indirect_a_R_100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_reg_indirect_a_R_101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_alt_base[256] = {
	alt_mov_a_base_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_base_P_000_R_00,
	alu_alt_base_P_001_R_00,
	alu_alt_base_P_010_R_00,
	alu_alt_base_P_011_R_00,
	alu_alt_base_P_100_R_00,
	alu_alt_base_P_101_R_00,
	alu_alt_base_P_110_R_00,
	alu_alt_base_P_111_R_00,
	alt_mov_a_base_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_base_P_000_R_01,
	alu_alt_base_P_001_R_01,
	alu_alt_base_P_010_R_01,
	alu_alt_base_P_011_R_01,
	alu_alt_base_P_100_R_01,
	alu_alt_base_P_101_R_01,
	alu_alt_base_P_110_R_01,
	alu_alt_base_P_111_R_01,
	alt_mov_a_base_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_base_P_000_R_10,
	alu_alt_base_P_001_R_10,
	alu_alt_base_P_010_R_10,
	alu_alt_base_P_011_R_10,
	alu_alt_base_P_100_R_10,
	alu_alt_base_P_101_R_10,
	alu_alt_base_P_110_R_10,
	alu_alt_base_P_111_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_base_a_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_base_a_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_base_a_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_alt_indexed[256] = {
	alt_mov_a_indexed_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_indexed_P_000_R_00,
	alu_alt_indexed_P_001_R_00,
	alu_alt_indexed_P_010_R_00,
	alu_alt_indexed_P_011_R_00,
	alu_alt_indexed_P_100_R_00,
	alu_alt_indexed_P_101_R_00,
	alu_alt_indexed_P_110_R_00,
	alu_alt_indexed_P_111_R_00,
	alt_mov_a_indexed_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_indexed_P_000_R_01,
	alu_alt_indexed_P_001_R_01,
	alu_alt_indexed_P_010_R_01,
	alu_alt_indexed_P_011_R_01,
	alu_alt_indexed_P_100_R_01,
	alu_alt_indexed_P_101_R_01,
	alu_alt_indexed_P_110_R_01,
	alu_alt_indexed_P_111_R_01,
	alt_mov_a_indexed_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_indexed_P_000_R_10,
	alu_alt_indexed_P_001_R_10,
	alu_alt_indexed_P_010_R_10,
	alu_alt_indexed_P_011_R_10,
	alu_alt_indexed_P_100_R_10,
	alu_alt_indexed_P_101_R_10,
	alu_alt_indexed_P_110_R_10,
	alu_alt_indexed_P_111_R_10,
	alt_mov_a_indexed_R_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_indexed_P_000_R_11,
	alu_alt_indexed_P_001_R_11,
	alu_alt_indexed_P_010_R_11,
	alu_alt_indexed_P_011_R_11,
	alu_alt_indexed_P_100_R_11,
	alu_alt_indexed_P_101_R_11,
	alu_alt_indexed_P_110_R_11,
	alu_alt_indexed_P_111_R_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_indexed_a_R_00,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_indexed_a_R_01,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_indexed_a_R_10,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_indexed_a_R_11,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_alt_regind[256] = {
	alt_mov_a_reg_indirect_R_000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_reg_indirect_P_000_R_000,
	alu_alt_reg_indirect_P_001_R_000,
	alu_alt_reg_indirect_P_010_R_000,
	alu_alt_reg_indirect_P_011_R_000,
	alu_alt_reg_indirect_P_100_R_000,
	alu_alt_reg_indirect_P_101_R_000,
	alu_alt_reg_indirect_P_110_R_000,
	alu_alt_reg_indirect_P_111_R_000,
	alt_mov_a_reg_indirect_R_001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_reg_indirect_P_000_R_001,
	alu_alt_reg_indirect_P_001_R_001,
	alu_alt_reg_indirect_P_010_R_001,
	alu_alt_reg_indirect_P_011_R_001,
	alu_alt_reg_indirect_P_100_R_001,
	alu_alt_reg_indirect_P_101_R_001,
	alu_alt_reg_indirect_P_110_R_001,
	alu_alt_reg_indirect_P_111_R_001,
	alt_mov_a_reg_indirect_R_010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_reg_indirect_P_000_R_010,
	alu_alt_reg_indirect_P_001_R_010,
	alu_alt_reg_indirect_P_010_R_010,
	alu_alt_reg_indirect_P_011_R_010,
	alu_alt_reg_indirect_P_100_R_010,
	alu_alt_reg_indirect_P_101_R_010,
	alu_alt_reg_indirect_P_110_R_010,
	alu_alt_reg_indirect_P_111_R_010,
	alt_mov_a_reg_indirect_R_011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_reg_indirect_P_000_R_011,
	alu_alt_reg_indirect_P_001_R_011,
	alu_alt_reg_indirect_P_010_R_011,
	alu_alt_reg_indirect_P_011_R_011,
	alu_alt_reg_indirect_P_100_R_011,
	alu_alt_reg_indirect_P_101_R_011,
	alu_alt_reg_indirect_P_110_R_011,
	alu_alt_reg_indirect_P_111_R_011,
	alt_mov_a_reg_indirect_R_100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_reg_indirect_P_000_R_100,
	alu_alt_reg_indirect_P_001_R_100,
	alu_alt_reg_indirect_P_010_R_100,
	alu_alt_reg_indirect_P_011_R_100,
	alu_alt_reg_indirect_P_100_R_100,
	alu_alt_reg_indirect_P_101_R_100,
	alu_alt_reg_indirect_P_110_R_100,
	alu_alt_reg_indirect_P_111_R_100,
	alt_mov_a_reg_indirect_R_101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_alt_reg_indirect_P_000_R_101,
	alu_alt_reg_indirect_P_001_R_101,
	alu_alt_reg_indirect_P_010_R_101,
	alu_alt_reg_indirect_P_011_R_101,
	alu_alt_reg_indirect_P_100_R_101,
	alu_alt_reg_indirect_P_101_R_101,
	alu_alt_reg_indirect_P_110_R_101,
	alu_alt_reg_indirect_P_111_R_101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_reg_indirect_a_R_000,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_reg_indirect_a_R_001,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_reg_indirect_a_R_010,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_reg_indirect_a_R_011,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_reg_indirect_a_R_100,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alt_mov_reg_indirect_a_R_101,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_mov_reg[256] = {
	mov_r_r_D_000_S_000,
	mov_r_r_D_000_S_001,
	mov_r_r_D_000_S_010,
	mov_r_r_D_000_S_011,
	mov_r_r_D_000_S_100,
	mov_r_r_D_000_S_101,
	mov_r_r_D_000_S_110,
	mov_r_r_D_000_S_111,
	movw_rp_rp_D_00_S_00,
	unimplemented,
	movw_rp_rp_D_00_S_01,
	unimplemented,
	movw_rp_rp_D_00_S_10,
	unimplemented,
	movw_rp_rp_D_00_S_11,
	unimplemented,
	mov_r_r_D_001_S_000,
	mov_r_r_D_001_S_001,
	mov_r_r_D_001_S_010,
	mov_r_r_D_001_S_011,
	mov_r_r_D_001_S_100,
	mov_r_r_D_001_S_101,
	mov_r_r_D_001_S_110,
	mov_r_r_D_001_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_r_r_D_010_S_000,
	mov_r_r_D_010_S_001,
	mov_r_r_D_010_S_010,
	mov_r_r_D_010_S_011,
	mov_r_r_D_010_S_100,
	mov_r_r_D_010_S_101,
	mov_r_r_D_010_S_110,
	mov_r_r_D_010_S_111,
	movw_rp_rp_D_01_S_00,
	unimplemented,
	movw_rp_rp_D_01_S_01,
	unimplemented,
	movw_rp_rp_D_01_S_10,
	unimplemented,
	movw_rp_rp_D_01_S_11,
	unimplemented,
	mov_r_r_D_011_S_000,
	mov_r_r_D_011_S_001,
	mov_r_r_D_011_S_010,
	mov_r_r_D_011_S_011,
	mov_r_r_D_011_S_100,
	mov_r_r_D_011_S_101,
	mov_r_r_D_011_S_110,
	mov_r_r_D_011_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_r_r_D_100_S_000,
	mov_r_r_D_100_S_001,
	mov_r_r_D_100_S_010,
	mov_r_r_D_100_S_011,
	mov_r_r_D_100_S_100,
	mov_r_r_D_100_S_101,
	mov_r_r_D_100_S_110,
	mov_r_r_D_100_S_111,
	movw_rp_rp_D_10_S_00,
	unimplemented,
	movw_rp_rp_D_10_S_01,
	unimplemented,
	movw_rp_rp_D_10_S_10,
	unimplemented,
	movw_rp_rp_D_10_S_11,
	unimplemented,
	mov_r_r_D_101_S_000,
	mov_r_r_D_101_S_001,
	mov_r_r_D_101_S_010,
	mov_r_r_D_101_S_011,
	mov_r_r_D_101_S_100,
	mov_r_r_D_101_S_101,
	mov_r_r_D_101_S_110,
	mov_r_r_D_101_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	mov_r_r_D_110_S_000,
	mov_r_r_D_110_S_001,
	mov_r_r_D_110_S_010,
	mov_r_r_D_110_S_011,
	mov_r_r_D_110_S_100,
	mov_r_r_D_110_S_101,
	mov_r_r_D_110_S_110,
	mov_r_r_D_110_S_111,
	movw_rp_rp_D_11_S_00,
	unimplemented,
	movw_rp_rp_D_11_S_01,
	unimplemented,
	movw_rp_rp_D_11_S_10,
	unimplemented,
	movw_rp_rp_D_11_S_11,
	unimplemented,
	mov_r_r_D_111_S_000,
	mov_r_r_D_111_S_001,
	mov_r_r_D_111_S_010,
	mov_r_r_D_111_S_011,
	mov_r_r_D_111_S_100,
	mov_r_r_D_111_S_101,
	mov_r_r_D_111_S_110,
	mov_r_r_D_111_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_xch_reg[256] = {
	xch_r_r_D_000_S_000,
	xch_r_r_D_000_S_001,
	xch_r_r_D_000_S_010,
	xch_r_r_D_000_S_011,
	xch_r_r_D_000_S_100,
	xch_r_r_D_000_S_101,
	xch_r_r_D_000_S_110,
	xch_r_r_D_000_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	xch_r_r_D_001_S_000,
	xch_r_r_D_001_S_001,
	xch_r_r_D_001_S_010,
	xch_r_r_D_001_S_011,
	xch_r_r_D_001_S_100,
	xch_r_r_D_001_S_101,
	xch_r_r_D_001_S_110,
	xch_r_r_D_001_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	xch_r_r_D_010_S_000,
	xch_r_r_D_010_S_001,
	xch_r_r_D_010_S_010,
	xch_r_r_D_010_S_011,
	xch_r_r_D_010_S_100,
	xch_r_r_D_010_S_101,
	xch_r_r_D_010_S_110,
	xch_r_r_D_010_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	xch_r_r_D_011_S_000,
	xch_r_r_D_011_S_001,
	xch_r_r_D_011_S_010,
	xch_r_r_D_011_S_011,
	xch_r_r_D_011_S_100,
	xch_r_r_D_011_S_101,
	xch_r_r_D_011_S_110,
	xch_r_r_D_011_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	xch_r_r_D_100_S_000,
	xch_r_r_D_100_S_001,
	xch_r_r_D_100_S_010,
	xch_r_r_D_100_S_011,
	xch_r_r_D_100_S_100,
	xch_r_r_D_100_S_101,
	xch_r_r_D_100_S_110,
	xch_r_r_D_100_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	xch_r_r_D_101_S_000,
	xch_r_r_D_101_S_001,
	xch_r_r_D_101_S_010,
	xch_r_r_D_101_S_011,
	xch_r_r_D_101_S_100,
	xch_r_r_D_101_S_101,
	xch_r_r_D_101_S_110,
	xch_r_r_D_101_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	xch_r_r_D_110_S_000,
	xch_r_r_D_110_S_001,
	xch_r_r_D_110_S_010,
	xch_r_r_D_110_S_011,
	xch_r_r_D_110_S_100,
	xch_r_r_D_110_S_101,
	xch_r_r_D_110_S_110,
	xch_r_r_D_110_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	xch_r_r_D_111_S_000,
	xch_r_r_D_111_S_001,
	xch_r_r_D_111_S_010,
	xch_r_r_D_111_S_011,
	xch_r_r_D_111_S_100,
	xch_r_r_D_111_S_101,
	xch_r_r_D_111_S_110,
	xch_r_r_D_111_S_111,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
};
static impl_fun impl_shr[256] = {
	rorc_r_N_000_R_000,
	rorc_r_N_000_R_001,
	rorc_r_N_000_R_010,
	rorc_r_N_000_R_011,
	rorc_r_N_000_R_100,
	rorc_r_N_000_R_101,
	rorc_r_N_000_R_110,
	rorc_r_N_000_R_111,
	rorc_r_N_001_R_000,
	rorc_r_N_001_R_001,
	rorc_r_N_001_R_010,
	rorc_r_N_001_R_011,
	rorc_r_N_001_R_100,
	rorc_r_N_001_R_101,
	rorc_r_N_001_R_110,
	rorc_r_N_001_R_111,
	rorc_r_N_010_R_000,
	rorc_r_N_010_R_001,
	rorc_r_N_010_R_010,
	rorc_r_N_010_R_011,
	rorc_r_N_010_R_100,
	rorc_r_N_010_R_101,
	rorc_r_N_010_R_110,
	rorc_r_N_010_R_111,
	rorc_r_N_011_R_000,
	rorc_r_N_011_R_001,
	rorc_r_N_011_R_010,
	rorc_r_N_011_R_011,
	rorc_r_N_011_R_100,
	rorc_r_N_011_R_101,
	rorc_r_N_011_R_110,
	rorc_r_N_011_R_111,
	rorc_r_N_100_R_000,
	rorc_r_N_100_R_001,
	rorc_r_N_100_R_010,
	rorc_r_N_100_R_011,
	rorc_r_N_100_R_100,
	rorc_r_N_100_R_101,
	rorc_r_N_100_R_110,
	rorc_r_N_100_R_111,
	rorc_r_N_101_R_000,
	rorc_r_N_101_R_001,
	rorc_r_N_101_R_010,
	rorc_r_N_101_R_011,
	rorc_r_N_101_R_100,
	rorc_r_N_101_R_101,
	rorc_r_N_101_R_110,
	rorc_r_N_101_R_111,
	rorc_r_N_110_R_000,
	rorc_r_N_110_R_001,
	rorc_r_N_110_R_010,
	rorc_r_N_110_R_011,
	rorc_r_N_110_R_100,
	rorc_r_N_110_R_101,
	rorc_r_N_110_R_110,
	rorc_r_N_110_R_111,
	rorc_r_N_111_R_000,
	rorc_r_N_111_R_001,
	rorc_r_N_111_R_010,
	rorc_r_N_111_R_011,
	rorc_r_N_111_R_100,
	rorc_r_N_111_R_101,
	rorc_r_N_111_R_110,
	rorc_r_N_111_R_111,
	ror_r_N_000_R_000,
	ror_r_N_000_R_001,
	ror_r_N_000_R_010,
	ror_r_N_000_R_011,
	ror_r_N_000_R_100,
	ror_r_N_000_R_101,
	ror_r_N_000_R_110,
	ror_r_N_000_R_111,
	ror_r_N_001_R_000,
	ror_r_N_001_R_001,
	ror_r_N_001_R_010,
	ror_r_N_001_R_011,
	ror_r_N_001_R_100,
	ror_r_N_001_R_101,
	ror_r_N_001_R_110,
	ror_r_N_001_R_111,
	ror_r_N_010_R_000,
	ror_r_N_010_R_001,
	ror_r_N_010_R_010,
	ror_r_N_010_R_011,
	ror_r_N_010_R_100,
	ror_r_N_010_R_101,
	ror_r_N_010_R_110,
	ror_r_N_010_R_111,
	ror_r_N_011_R_000,
	ror_r_N_011_R_001,
	ror_r_N_011_R_010,
	ror_r_N_011_R_011,
	ror_r_N_011_R_100,
	ror_r_N_011_R_101,
	ror_r_N_011_R_110,
	ror_r_N_011_R_111,
	ror_r_N_100_R_000,
	ror_r_N_100_R_001,
	ror_r_N_100_R_010,
	ror_r_N_100_R_011,
	ror_r_N_100_R_100,
	ror_r_N_100_R_101,
	ror_r_N_100_R_110,
	ror_r_N_100_R_111,
	ror_r_N_101_R_000,
	ror_r_N_101_R_001,
	ror_r_N_101_R_010,
	ror_r_N_101_R_011,
	ror_r_N_101_R_100,
	ror_r_N_101_R_101,
	ror_r_N_101_R_110,
	ror_r_N_101_R_111,
	ror_r_N_110_R_000,
	ror_r_N_110_R_001,
	ror_r_N_110_R_010,
	ror_r_N_110_R_011,
	ror_r_N_110_R_100,
	ror_r_N_110_R_101,
	ror_r_N_110_R_110,
	ror_r_N_110_R_111,
	ror_r_N_111_R_000,
	ror_r_N_111_R_001,
	ror_r_N_111_R_010,
	ror_r_N_111_R_011,
	ror_r_N_111_R_100,
	ror_r_N_111_R_101,
	ror_r_N_111_R_110,
	ror_r_N_111_R_111,
	shr_r_N_000_R_000,
	shr_r_N_000_R_001,
	shr_r_N_000_R_010,
	shr_r_N_000_R_011,
	shr_r_N_000_R_100,
	shr_r_N_000_R_101,
	shr_r_N_000_R_110,
	shr_r_N_000_R_111,
	shr_r_N_001_R_000,
	shr_r_N_001_R_001,
	shr_r_N_001_R_010,
	shr_r_N_001_R_011,
	shr_r_N_001_R_100,
	shr_r_N_001_R_101,
	shr_r_N_001_R_110,
	shr_r_N_001_R_111,
	shr_r_N_010_R_000,
	shr_r_N_010_R_001,
	shr_r_N_010_R_010,
	shr_r_N_010_R_011,
	shr_r_N_010_R_100,
	shr_r_N_010_R_101,
	shr_r_N_010_R_110,
	shr_r_N_010_R_111,
	shr_r_N_011_R_000,
	shr_r_N_011_R_001,
	shr_r_N_011_R_010,
	shr_r_N_011_R_011,
	shr_r_N_011_R_100,
	shr_r_N_011_R_101,
	shr_r_N_011_R_110,
	shr_r_N_011_R_111,
	shr_r_N_100_R_000,
	shr_r_N_100_R_001,
	shr_r_N_100_R_010,
	shr_r_N_100_R_011,
	shr_r_N_100_R_100,
	shr_r_N_100_R_101,
	shr_r_N_100_R_110,
	shr_r_N_100_R_111,
	shr_r_N_101_R_000,
	shr_r_N_101_R_001,
	shr_r_N_101_R_010,
	shr_r_N_101_R_011,
	shr_r_N_101_R_100,
	shr_r_N_101_R_101,
	shr_r_N_101_R_110,
	shr_r_N_101_R_111,
	shr_r_N_110_R_000,
	shr_r_N_110_R_001,
	shr_r_N_110_R_010,
	shr_r_N_110_R_011,
	shr_r_N_110_R_100,
	shr_r_N_110_R_101,
	shr_r_N_110_R_110,
	shr_r_N_110_R_111,
	shr_r_N_111_R_000,
	shr_r_N_111_R_001,
	shr_r_N_111_R_010,
	shr_r_N_111_R_011,
	shr_r_N_111_R_100,
	shr_r_N_111_R_101,
	shr_r_N_111_R_110,
	shr_r_N_111_R_111,
	shrw_rp_N_000_R_000,
	shrw_rp_N_000_R_001,
	shrw_rp_N_000_R_010,
	shrw_rp_N_000_R_011,
	shrw_rp_N_000_R_100,
	shrw_rp_N_000_R_101,
	shrw_rp_N_000_R_110,
	shrw_rp_N_000_R_111,
	shrw_rp_N_001_R_000,
	shrw_rp_N_001_R_001,
	shrw_rp_N_001_R_010,
	shrw_rp_N_001_R_011,
	shrw_rp_N_001_R_100,
	shrw_rp_N_001_R_101,
	shrw_rp_N_001_R_110,
	shrw_rp_N_001_R_111,
	shrw_rp_N_010_R_000,
	shrw_rp_N_010_R_001,
	shrw_rp_N_010_R_010,
	shrw_rp_N_010_R_011,
	shrw_rp_N_010_R_100,
	shrw_rp_N_010_R_101,
	shrw_rp_N_010_R_110,
	shrw_rp_N_010_R_111,
	shrw_rp_N_011_R_000,
	shrw_rp_N_011_R_001,
	shrw_rp_N_011_R_010,
	shrw_rp_N_011_R_011,
	shrw_rp_N_011_R_100,
	shrw_rp_N_011_R_101,
	shrw_rp_N_011_R_110,
	shrw_rp_N_011_R_111,
	shrw_rp_N_100_R_000,
	shrw_rp_N_100_R_001,
	shrw_rp_N_100_R_010,
	shrw_rp_N_100_R_011,
	shrw_rp_N_100_R_100,
	shrw_rp_N_100_R_101,
	shrw_rp_N_100_R_110,
	shrw_rp_N_100_R_111,
	shrw_rp_N_101_R_000,
	shrw_rp_N_101_R_001,
	shrw_rp_N_101_R_010,
	shrw_rp_N_101_R_011,
	shrw_rp_N_101_R_100,
	shrw_rp_N_101_R_101,
	shrw_rp_N_101_R_110,
	shrw_rp_N_101_R_111,
	shrw_rp_N_110_R_000,
	shrw_rp_N_110_R_001,
	shrw_rp_N_110_R_010,
	shrw_rp_N_110_R_011,
	shrw_rp_N_110_R_100,
	shrw_rp_N_110_R_101,
	shrw_rp_N_110_R_110,
	shrw_rp_N_110_R_111,
	shrw_rp_N_111_R_000,
	shrw_rp_N_111_R_001,
	shrw_rp_N_111_R_010,
	shrw_rp_N_111_R_011,
	shrw_rp_N_111_R_100,
	shrw_rp_N_111_R_101,
	shrw_rp_N_111_R_110,
	shrw_rp_N_111_R_111,
};
static impl_fun impl_shl[256] = {
	rolc_r_N_000_R_000,
	rolc_r_N_000_R_001,
	rolc_r_N_000_R_010,
	rolc_r_N_000_R_011,
	rolc_r_N_000_R_100,
	rolc_r_N_000_R_101,
	rolc_r_N_000_R_110,
	rolc_r_N_000_R_111,
	rolc_r_N_001_R_000,
	rolc_r_N_001_R_001,
	rolc_r_N_001_R_010,
	rolc_r_N_001_R_011,
	rolc_r_N_001_R_100,
	rolc_r_N_001_R_101,
	rolc_r_N_001_R_110,
	rolc_r_N_001_R_111,
	rolc_r_N_010_R_000,
	rolc_r_N_010_R_001,
	rolc_r_N_010_R_010,
	rolc_r_N_010_R_011,
	rolc_r_N_010_R_100,
	rolc_r_N_010_R_101,
	rolc_r_N_010_R_110,
	rolc_r_N_010_R_111,
	rolc_r_N_011_R_000,
	rolc_r_N_011_R_001,
	rolc_r_N_011_R_010,
	rolc_r_N_011_R_011,
	rolc_r_N_011_R_100,
	rolc_r_N_011_R_101,
	rolc_r_N_011_R_110,
	rolc_r_N_011_R_111,
	rolc_r_N_100_R_000,
	rolc_r_N_100_R_001,
	rolc_r_N_100_R_010,
	rolc_r_N_100_R_011,
	rolc_r_N_100_R_100,
	rolc_r_N_100_R_101,
	rolc_r_N_100_R_110,
	rolc_r_N_100_R_111,
	rolc_r_N_101_R_000,
	rolc_r_N_101_R_001,
	rolc_r_N_101_R_010,
	rolc_r_N_101_R_011,
	rolc_r_N_101_R_100,
	rolc_r_N_101_R_101,
	rolc_r_N_101_R_110,
	rolc_r_N_101_R_111,
	rolc_r_N_110_R_000,
	rolc_r_N_110_R_001,
	rolc_r_N_110_R_010,
	rolc_r_N_110_R_011,
	rolc_r_N_110_R_100,
	rolc_r_N_110_R_101,
	rolc_r_N_110_R_110,
	rolc_r_N_110_R_111,
	rolc_r_N_111_R_000,
	rolc_r_N_111_R_001,
	rolc_r_N_111_R_010,
	rolc_r_N_111_R_011,
	rolc_r_N_111_R_100,
	rolc_r_N_111_R_101,
	rolc_r_N_111_R_110,
	rolc_r_N_111_R_111,
	rol_r_N_000_R_000,
	rol_r_N_000_R_001,
	rol_r_N_000_R_010,
	rol_r_N_000_R_011,
	rol_r_N_000_R_100,
	rol_r_N_000_R_101,
	rol_r_N_000_R_110,
	rol_r_N_000_R_111,
	rol_r_N_001_R_000,
	rol_r_N_001_R_001,
	rol_r_N_001_R_010,
	rol_r_N_001_R_011,
	rol_r_N_001_R_100,
	rol_r_N_001_R_101,
	rol_r_N_001_R_110,
	rol_r_N_001_R_111,
	rol_r_N_010_R_000,
	rol_r_N_010_R_001,
	rol_r_N_010_R_010,
	rol_r_N_010_R_011,
	rol_r_N_010_R_100,
	rol_r_N_010_R_101,
	rol_r_N_010_R_110,
	rol_r_N_010_R_111,
	rol_r_N_011_R_000,
	rol_r_N_011_R_001,
	rol_r_N_011_R_010,
	rol_r_N_011_R_011,
	rol_r_N_011_R_100,
	rol_r_N_011_R_101,
	rol_r_N_011_R_110,
	rol_r_N_011_R_111,
	rol_r_N_100_R_000,
	rol_r_N_100_R_001,
	rol_r_N_100_R_010,
	rol_r_N_100_R_011,
	rol_r_N_100_R_100,
	rol_r_N_100_R_101,
	rol_r_N_100_R_110,
	rol_r_N_100_R_111,
	rol_r_N_101_R_000,
	rol_r_N_101_R_001,
	rol_r_N_101_R_010,
	rol_r_N_101_R_011,
	rol_r_N_101_R_100,
	rol_r_N_101_R_101,
	rol_r_N_101_R_110,
	rol_r_N_101_R_111,
	rol_r_N_110_R_000,
	rol_r_N_110_R_001,
	rol_r_N_110_R_010,
	rol_r_N_110_R_011,
	rol_r_N_110_R_100,
	rol_r_N_110_R_101,
	rol_r_N_110_R_110,
	rol_r_N_110_R_111,
	rol_r_N_111_R_000,
	rol_r_N_111_R_001,
	rol_r_N_111_R_010,
	rol_r_N_111_R_011,
	rol_r_N_111_R_100,
	rol_r_N_111_R_101,
	rol_r_N_111_R_110,
	rol_r_N_111_R_111,
	shl_r_N_000_R_000,
	shl_r_N_000_R_001,
	shl_r_N_000_R_010,
	shl_r_N_000_R_011,
	shl_r_N_000_R_100,
	shl_r_N_000_R_101,
	shl_r_N_000_R_110,
	shl_r_N_000_R_111,
	shl_r_N_001_R_000,
	shl_r_N_001_R_001,
	shl_r_N_001_R_010,
	shl_r_N_001_R_011,
	shl_r_N_001_R_100,
	shl_r_N_001_R_101,
	shl_r_N_001_R_110,
	shl_r_N_001_R_111,
	shl_r_N_010_R_000,
	shl_r_N_010_R_001,
	shl_r_N_010_R_010,
	shl_r_N_010_R_011,
	shl_r_N_010_R_100,
	shl_r_N_010_R_101,
	shl_r_N_010_R_110,
	shl_r_N_010_R_111,
	shl_r_N_011_R_000,
	shl_r_N_011_R_001,
	shl_r_N_011_R_010,
	shl_r_N_011_R_011,
	shl_r_N_011_R_100,
	shl_r_N_011_R_101,
	shl_r_N_011_R_110,
	shl_r_N_011_R_111,
	shl_r_N_100_R_000,
	shl_r_N_100_R_001,
	shl_r_N_100_R_010,
	shl_r_N_100_R_011,
	shl_r_N_100_R_100,
	shl_r_N_100_R_101,
	shl_r_N_100_R_110,
	shl_r_N_100_R_111,
	shl_r_N_101_R_000,
	shl_r_N_101_R_001,
	shl_r_N_101_R_010,
	shl_r_N_101_R_011,
	shl_r_N_101_R_100,
	shl_r_N_101_R_101,
	shl_r_N_101_R_110,
	shl_r_N_101_R_111,
	shl_r_N_110_R_000,
	shl_r_N_110_R_001,
	shl_r_N_110_R_010,
	shl_r_N_110_R_011,
	shl_r_N_110_R_100,
	shl_r_N_110_R_101,
	shl_r_N_110_R_110,
	shl_r_N_110_R_111,
	shl_r_N_111_R_000,
	shl_r_N_111_R_001,
	shl_r_N_111_R_010,
	shl_r_N_111_R_011,
	shl_r_N_111_R_100,
	shl_r_N_111_R_101,
	shl_r_N_111_R_110,
	shl_r_N_111_R_111,
	shlw_rp_N_000_R_000,
	shlw_rp_N_000_R_001,
	shlw_rp_N_000_R_010,
	shlw_rp_N_000_R_011,
	shlw_rp_N_000_R_100,
	shlw_rp_N_000_R_101,
	shlw_rp_N_000_R_110,
	shlw_rp_N_000_R_111,
	shlw_rp_N_001_R_000,
	shlw_rp_N_001_R_001,
	shlw_rp_N_001_R_010,
	shlw_rp_N_001_R_011,
	shlw_rp_N_001_R_100,
	shlw_rp_N_001_R_101,
	shlw_rp_N_001_R_110,
	shlw_rp_N_001_R_111,
	shlw_rp_N_010_R_000,
	shlw_rp_N_010_R_001,
	shlw_rp_N_010_R_010,
	shlw_rp_N_010_R_011,
	shlw_rp_N_010_R_100,
	shlw_rp_N_010_R_101,
	shlw_rp_N_010_R_110,
	shlw_rp_N_010_R_111,
	shlw_rp_N_011_R_000,
	shlw_rp_N_011_R_001,
	shlw_rp_N_011_R_010,
	shlw_rp_N_011_R_011,
	shlw_rp_N_011_R_100,
	shlw_rp_N_011_R_101,
	shlw_rp_N_011_R_110,
	shlw_rp_N_011_R_111,
	shlw_rp_N_100_R_000,
	shlw_rp_N_100_R_001,
	shlw_rp_N_100_R_010,
	shlw_rp_N_100_R_011,
	shlw_rp_N_100_R_100,
	shlw_rp_N_100_R_101,
	shlw_rp_N_100_R_110,
	shlw_rp_N_100_R_111,
	shlw_rp_N_101_R_000,
	shlw_rp_N_101_R_001,
	shlw_rp_N_101_R_010,
	shlw_rp_N_101_R_011,
	shlw_rp_N_101_R_100,
	shlw_rp_N_101_R_101,
	shlw_rp_N_101_R_110,
	shlw_rp_N_101_R_111,
	shlw_rp_N_110_R_000,
	shlw_rp_N_110_R_001,
	shlw_rp_N_110_R_010,
	shlw_rp_N_110_R_011,
	shlw_rp_N_110_R_100,
	shlw_rp_N_110_R_101,
	shlw_rp_N_110_R_110,
	shlw_rp_N_110_R_111,
	shlw_rp_N_111_R_000,
	shlw_rp_N_111_R_001,
	shlw_rp_N_111_R_010,
	shlw_rp_N_111_R_011,
	shlw_rp_N_111_R_100,
	shlw_rp_N_111_R_101,
	shlw_rp_N_111_R_110,
	shlw_rp_N_111_R_111,
};
static impl_fun impl_main[256] = {
	nop,
	sfr_prefix,
	bit1_prefix,
	bit2_prefix,
	unimplemented,
	muldiv_prefix,
	base_prefix,
	unimplemented,
	sfrbit_prefix,
	spmov_prefix,
	indexed_prefix,
	movw_sfrp_immed,
	movw_sadrp_word,
	unimplemented,
	adjba,
	adjbs,
	mov_a_sfr,
	movw_ax_sfr,
	mov_sfr_a,
	movw_sfr_ax,
	br_rel,
	unimplemented,
	regind_prefix,
	unimplemented,
	unimplemented,
	unimplemented,
	movw_saddr_ax,
	unimplemented,
	movw_ax_saddr,
	alu_ax_saddr_P_01,
	alu_ax_saddr_P_10,
	alu_ax_saddr_P_11,
	mov_a_saddr,
	unimplemented,
	mov_saddr_a,
	unimplemented,
	mov_reg_prefix,
	xch_reg_prefix,
	inc_saddr,
	dec_saddr,
	call_long,
	push_sfr,
	unimplemented,
	mov_sfr_immed,
	br_abs,
	alu_ax_immed_P_01,
	alu_ax_immed_P_10,
	alu_ax_immed_P_11,
	shr_prefix,
	shl_prefix,
	dbnz_r_R_0,
	dbnz_r_R_1,
	pop_rp_P_00,
	pop_rp_P_01,
	pop_rp_P_10,
	pop_rp_P_11,
	mov_saddr_saddr,
	xch_saddr_saddr,
	mov_saddr_immed,
	unimplemented,
	push_rp_P_00,
	push_rp_P_01,
	push_rp_P_10,
	push_rp_P_11,
	clr1_cy,
	set1_cy,
	not1_cy,
	pop_sfr,
	incw_rp_P_00,
	incw_rp_P_01,
	incw_rp_P_10,
	incw_rp_P_11,
	unimplemented,
	unimplemented,
	di,
	ei,
	decw_rp_P_00,
	decw_rp_P_01,
	decw_rp_P_10,
	decw_rp_P_11,
	mov_reg_indirect_a_short_R_000,
	mov_reg_indirect_a_short_R_001,
	mov_reg_indirect_a_short_R_010,
	mov_reg_indirect_a_short_R_011,
	mov_reg_indirect_a_short_R_100,
	mov_reg_indirect_a_short_R_101,
	ret,
	reti,
	mov_a_reg_indirect_short_R_000,
	mov_a_reg_indirect_short_R_001,
	mov_a_reg_indirect_short_R_010,
	mov_a_reg_indirect_short_R_011,
	mov_a_reg_indirect_short_R_100,
	mov_a_reg_indirect_short_R_101,
	unimplemented,
	unimplemented,
	movw_rp_immed_P_00,
	unimplemented,
	movw_rp_immed_P_01,
	unimplemented,
	movw_rp_immed_P_10,
	unimplemented,
	movw_rp_immed_P_11,
	unimplemented,
	alu_saddr_immed_P_000,
	alu_saddr_immed_P_001,
	alu_saddr_immed_P_010,
	alu_saddr_immed_P_011,
	alu_saddr_immed_P_100,
	alu_saddr_immed_P_101,
	alu_saddr_immed_P_110,
	alu_saddr_immed_P_111,
	bt_saddr_B_000,
	bt_saddr_B_001,
	bt_saddr_B_010,
	bt_saddr_B_011,
	bt_saddr_B_100,
	bt_saddr_B_101,
	bt_saddr_B_110,
	bt_saddr_B_111,
	alu_saddr_saddr_P_000,
	alu_saddr_saddr_P_001,
	alu_saddr_saddr_P_010,
	alu_saddr_saddr_P_011,
	alu_saddr_saddr_P_100,
	alu_saddr_saddr_P_101,
	alu_saddr_saddr_P_110,
	alu_saddr_saddr_P_111,
	bcc_F_0_S_0,
	bcc_F_0_S_1,
	bcc_F_1_S_0,
	bcc_F_1_S_1,
	unimplemented,
	unimplemented,
	unimplemented,
	unimplemented,
	alu_r_r_P_000,
	alu_r_r_P_001,
	alu_r_r_P_010,
	alu_r_r_P_011,
	alu_r_r_P_100,
	alu_r_r_P_101,
	alu_r_r_P_110,
	alu_r_r_P_111,
	call_short_A_000,
	call_short_A_001,
	call_short_A_010,
	call_short_A_011,
	call_short_A_100,
	call_short_A_101,
	call_short_A_110,
	call_short_A_111,
	alu_a_saddr_P_000,
	alu_a_saddr_P_001,
	alu_a_saddr_P_010,
	alu_a_saddr_P_011,
	alu_a_saddr_P_100,
	alu_a_saddr_P_101,
	alu_a_saddr_P_110,
	alu_a_saddr_P_111,
	clr1_saddr_B_000,
	clr1_saddr_B_001,
	clr1_saddr_B_010,
	clr1_saddr_B_011,
	clr1_saddr_B_100,
	clr1_saddr_B_101,
	clr1_saddr_B_110,
	clr1_saddr_B_111,
	alu_immed_P_000,
	alu_immed_P_001,
	alu_immed_P_010,
	alu_immed_P_011,
	alu_immed_P_100,
	alu_immed_P_101,
	alu_immed_P_110,
	alu_immed_P_111,
	set1_saddr_B_000,
	set1_saddr_B_001,
	set1_saddr_B_010,
	set1_saddr_B_011,
	set1_saddr_B_100,
	set1_saddr_B_101,
	set1_saddr_B_110,
	set1_saddr_B_111,
	mov_r_immed_R_000,
	mov_r_immed_R_001,
	mov_r_immed_R_010,
	mov_r_immed_R_011,
	mov_r_immed_R_100,
	mov_r_immed_R_101,
	mov_r_immed_R_110,
	mov_r_immed_R_111,
	inc_r_R_000,
	inc_r_R_001,
	inc_r_R_010,
	inc_r_R_011,
	inc_r_R_100,
	inc_r_R_101,
	inc_r_R_110,
	inc_r_R_111,
	dec_r_R_000,
	dec_r_R_001,
	dec_r_R_010,
	dec_r_R_011,
	dec_r_R_100,
	dec_r_R_101,
	dec_r_R_110,
	dec_r_R_111,
	mov_a_r_R_000,
	mov_a_r_R_001,
	mov_a_r_R_010,
	mov_a_r_R_011,
	mov_a_r_R_100,
	mov_a_r_R_101,
	mov_a_r_R_110,
	mov_a_r_R_111,
	xch_a_r_R_000,
	xch_a_r_R_001,
	xch_a_r_R_010,
	xch_a_r_R_011,
	xch_a_r_R_100,
	xch_a_r_R_101,
	xch_a_r_R_110,
	xch_a_r_R_111,
	call_table_T_00000,
	call_table_T_00001,
	call_table_T_00010,
	call_table_T_00011,
	call_table_T_00100,
	call_table_T_00101,
	call_table_T_00110,
	call_table_T_00111,
	call_table_T_01000,
	call_table_T_01001,
	call_table_T_01010,
	call_table_T_01011,
	call_table_T_01100,
	call_table_T_01101,
	call_table_T_01110,
	call_table_T_01111,
	call_table_T_10000,
	call_table_T_10001,
	call_table_T_10010,
	call_table_T_10011,
	call_table_T_10100,
	call_table_T_10101,
	call_table_T_10110,
	call_table_T_10111,
	call_table_T_11000,
	call_table_T_11001,
	call_table_T_11010,
	call_table_T_11011,
	call_table_T_11100,
	call_table_T_11101,
	call_table_T_11110,
	call_table_T_11111,
};
void upd78k2_execute(upd78k2_context *context, uint32_t target_cycle)
{
	uint16_t upd78k2_interrupt_vector_addr;
	uint16_t upd78k2_interrupt_pending;
	uint8_t mem_write_no_exp_offset;
	uint8_t iram_write_normal_iram;
	uint8_t iram_write_regnum;
	uint8_t push_word_tmp;
	uint8_t mem_read_no_exp_offset;
	uint8_t iram_read_normal_iram;
	uint32_t upd78k2_interrupt_cmp_tmp32__;
	uint8_t upd78k2_interrupt_cmp_tmp8__;
	uint32_t upd78k2_run_op_cmp_tmp32__;
	uint8_t upd78k2_run_op_cmp_tmp8__;
	upd78k2_sync_cycle(context, target_cycle);
	if (context->breakpoints) {
		while (context->cycles < target_cycle)
		{
			if (context->cycles >= context->sync_cycle) {
				upd78k2_sync_cycle(context, target_cycle);
			}
	if (context->cycles >= context->int_cycle) {
	upd78k2_sync_cycle(context, target_cycle);
	if (context->int_enable) {
	upd78k2_interrupt_pending = ~context->mk0;
	if (context->int_priority_flag == 0) {
	context->scratch1 = ~context->pr0;
	upd78k2_interrupt_pending = context->scratch1 & upd78k2_interrupt_pending;
	}
	upd78k2_interrupt_pending = context->if0 & upd78k2_interrupt_pending;
	if (upd78k2_interrupt_pending) {
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->sp = context->sp - 1;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch1 = context->psw;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->iram[mem_write_no_exp_offset] = context->psw;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->main[iram_write_regnum] = context->psw;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch1 = context->psw;
	upd78k2_write_8(context);
	}
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->scratch1 = upd78k2_interrupt_pending;
	upd78k2_calc_vector(context);
	upd78k2_interrupt_vector_addr = context->scratch1;
	if (upd78k2_interrupt_vector_addr >= 65024) {
	if (upd78k2_interrupt_vector_addr >= 65280) {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = upd78k2_interrupt_vector_addr;
	upd78k2_read_8(context);
	}
	context->pc = context->scratch1;
	upd78k2_interrupt_vector_addr = 1 + upd78k2_interrupt_vector_addr;
	if (upd78k2_interrupt_vector_addr >= 65024) {
	if (upd78k2_interrupt_vector_addr >= 65280) {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = upd78k2_interrupt_vector_addr;
	upd78k2_read_8(context);
	}
	context->scratch1 = context->scratch1 << 8;
	context->pc = context->scratch1 | context->pc;
	context->int_enable = 0;
	}
	}
	}
			uint32_t debug_pc = context->pc - 0;
			char key_buf[6];
			debug_handler handler = tern_find_ptr(context->breakpoints, tern_int_key(debug_pc, key_buf));
			if (handler) {
				handler(context, debug_pc);
			}
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_main[context->scratch1](context, target_cycle);
	}
	} else {
	while (context->cycles < target_cycle)
	{
		if (context->cycles >= context->sync_cycle) {
			upd78k2_sync_cycle(context, target_cycle);
		}
	if (context->cycles >= context->int_cycle) {
	upd78k2_sync_cycle(context, target_cycle);
	if (context->int_enable) {
	upd78k2_interrupt_pending = ~context->mk0;
	if (context->int_priority_flag == 0) {
	context->scratch1 = ~context->pr0;
	upd78k2_interrupt_pending = context->scratch1 & upd78k2_interrupt_pending;
	}
	upd78k2_interrupt_pending = context->if0 & upd78k2_interrupt_pending;
	if (upd78k2_interrupt_pending) {
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->sp = context->sp - 1;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch1 = context->psw;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->iram[mem_write_no_exp_offset] = context->psw;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->main[iram_write_regnum] = context->psw;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->psw = 0;
	if (context->int_enable) {
		context->psw |= 1 << 7;
	}
	if (context->zflag) {
		context->psw |= 1 << 6;
	}
	if (context->int_priority_flag) {
		context->psw |= 1 << 1;
	}
	if (context->rbs & (1 << 1)) {
		context->psw |= 1 << 5;
	}
	if (context->rbs & (1 << 0)) {
		context->psw |= 1 << 3;
	}
	if (context->chflags & (1 << 3)) {
		context->psw |= 1 << 4;
	}
	if (context->chflags & (1 << 7)) {
		context->psw |= 1 << 0;
	}
	context->scratch1 = context->psw;
	upd78k2_write_8(context);
	}
	push_word_tmp = context->pc >> 8;
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = push_word_tmp;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = push_word_tmp;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = push_word_tmp;
	upd78k2_write_8(context);
	}
	context->sp = context->sp - 1;
	if (context->sp >= 65024) {
	if (context->sp >= 65280) {
	mem_write_no_exp_offset = context->sp;
	context->scratch2 = mem_write_no_exp_offset + 65280;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	} else {
	mem_write_no_exp_offset = context->sp;
	iram_write_normal_iram = 1;
	if (mem_write_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_write_no_exp_offset >= 248) {
	iram_write_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_write_no_exp_offset >= 240) {
	if (mem_write_no_exp_offset >= 248) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_write_no_exp_offset >= 232) {
	if (mem_write_no_exp_offset >= 240) {
	} else {
	iram_write_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_write_no_exp_offset >= 232) {
	} else {
	iram_write_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_write_normal_iram) {
	context->iram[mem_write_no_exp_offset] = context->pc;
	} else {
	iram_write_regnum = mem_write_no_exp_offset & 8;
	context->main[iram_write_regnum] = context->pc;
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch2 = context->sp;
	context->scratch1 = context->pc;
	upd78k2_write_8(context);
	}
	context->scratch1 = upd78k2_interrupt_pending;
	upd78k2_calc_vector(context);
	upd78k2_interrupt_vector_addr = context->scratch1;
	if (upd78k2_interrupt_vector_addr >= 65024) {
	if (upd78k2_interrupt_vector_addr >= 65280) {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = upd78k2_interrupt_vector_addr;
	upd78k2_read_8(context);
	}
	context->pc = context->scratch1;
	upd78k2_interrupt_vector_addr = 1 + upd78k2_interrupt_vector_addr;
	if (upd78k2_interrupt_vector_addr >= 65024) {
	if (upd78k2_interrupt_vector_addr >= 65280) {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = upd78k2_interrupt_vector_addr;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = upd78k2_interrupt_vector_addr;
	upd78k2_read_8(context);
	}
	context->scratch1 = context->scratch1 << 8;
	context->pc = context->scratch1 | context->pc;
	context->int_enable = 0;
	}
	}
	}
	if (context->pc >= 65024) {
	if (context->pc >= 65280) {
	mem_read_no_exp_offset = context->pc;
	context->scratch1 = mem_read_no_exp_offset + 65280;
	upd78k2_read_8(context);
	} else {
	mem_read_no_exp_offset = context->pc;
	iram_read_normal_iram = 1;
	if (mem_read_no_exp_offset >= 224) {
	switch(context->rbs)
	{
	case 0U: {
	if (mem_read_no_exp_offset >= 248) {
	iram_read_normal_iram = 0;
	}
	break;
	}
	case 1U: {
	if (mem_read_no_exp_offset >= 240) {
	if (mem_read_no_exp_offset >= 248) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 2U: {
	if (mem_read_no_exp_offset >= 232) {
	if (mem_read_no_exp_offset >= 240) {
	} else {
	iram_read_normal_iram = 0;
	}
	}
	break;
	}
	case 3U: {
	if (mem_read_no_exp_offset >= 232) {
	} else {
	iram_read_normal_iram = 0;
	}
	break;
	}
	}
	}
	if (iram_read_normal_iram) {
	context->scratch1 = context->iram[mem_read_no_exp_offset];
	} else {
	context->scratch1 = mem_read_no_exp_offset & 7;
	context->scratch1 = context->main[context->scratch1];
	}
	context->cycles += context->opts->gen.clock_divider * 2;
	}
	} else {
	context->scratch1 = context->pc;
	upd78k2_read_8(context);
	}
	context->pc = 1 + context->pc;
	impl_main[context->scratch1](context, target_cycle);
	}
	}
}
