/* Autogenerated file, DO NOT EDIT manually! generated by perf-metricset-codegen.py
 *
 * Copyright (c) 2018 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <assert.h>

#include "i915_drm.h"

#include "i915_perf_metrics_acmgt1.h"
#include "i915_perf_equations.h"
#include "i915_perf_registers_acmgt1.h"

static bool acmgt1_render_basic_Sampler20Bottleneck_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_render_basic_Sampler20Busy_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_render_basic_SamplerBottleneck_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_render_basic_SamplersBusy_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_render_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics Basic - aggregation approximation";
    metric_set->symbol_name = "RenderBasic";
    metric_set->hw_config_guid = "f5b8f05e-c84c-4f1c-bb05-68fbea73879b";
    metric_set->counters = calloc(30, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_render_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__render_basic__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__render_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__render_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__render_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__render_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__render_basic__gti_read_throughput__read,
                .max_uint64 = acmgt1__render_basic__gti_read_throughput__max,
                .group = "Memory",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__render_basic__gti_write_throughput__read,
                .max_uint64 = acmgt1__render_basic__gti_write_throughput__max,
                .group = "Memory",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS Send Pipe Active",
                .symbol_name = "PsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__ps_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "Sampler20 Bottleneck",
                .symbol_name = "Sampler20Bottleneck",
                .desc = "The percentage of time in which Slice2 Sampler0 has been slowing down the pipe when processing XVE requests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__sampler20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_render_basic_Sampler20Bottleneck_availability,
            },

            {
                .name = "Sampler Slice2 Xe Core0 is busy",
                .symbol_name = "Sampler20Busy",
                .desc = "The percentage of time when sampler slice2 Xe core0 is busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__sampler20_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_render_basic_Sampler20Busy_availability,
            },

            {
                .name = "Samplers Bottleneck",
                .symbol_name = "SamplerBottleneck",
                .desc = "The percentage of time in which samplers have been slowing down the pipe when processing XVE requests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__sampler_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_render_basic_SamplerBottleneck_availability,
            },

            {
                .name = "Sampler Texels Misses",
                .symbol_name = "SamplerTexelMisses",
                .desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt1__render_basic__sampler_texel_misses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Sampler Texels",
                .symbol_name = "SamplerTexels",
                .desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt1__render_basic__sampler_texels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },

            {
                .name = "Samplers Busy",
                .symbol_name = "SamplersBusy",
                .desc = "The percentage of time in which samplers or L1 cache are not idle.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__samplers_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_render_basic_SamplersBusy_availability,
            },

            {
                .name = "Samples Blended",
                .symbol_name = "SamplesBlended",
                .desc = "The total number of blended samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt1__render_basic__samples_blended__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Samples Written",
                .symbol_name = "SamplesWritten",
                .desc = "The total number of samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt1__render_basic__samples_written__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__render_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__render_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__render_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__render_basic__slm_reads__read,
                .max_uint64 = acmgt1__render_basic__slm_reads__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__render_basic__slm_writes__read,
                .max_uint64 = acmgt1__render_basic__slm_writes__max,
                .group = "L1Cache",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS Send Pipe Active",
                .symbol_name = "VsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__vs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 30);
}


static void
acmgt1_add_compute_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Compute Metrics Basic";
    metric_set->symbol_name = "ComputeBasic";
    metric_set->hw_config_guid = "53ee6271-905c-4b2a-b449-9117ffd10a48";
    metric_set->counters = calloc(25, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_compute_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__compute_basic__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__compute_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__compute_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__compute_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__compute_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__compute_basic__gti_read_throughput__read,
                .max_uint64 = acmgt1__compute_basic__gti_read_throughput__max,
                .group = "Memory",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__compute_basic__gti_write_throughput__read,
                .max_uint64 = acmgt1__compute_basic__gti_write_throughput__max,
                .group = "Memory",
            },

            {
                .name = "Send Pipe Active",
                .symbol_name = "SendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__compute_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__compute_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__compute_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__compute_basic__slm_reads__read,
                .max_uint64 = acmgt1__compute_basic__slm_reads__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__compute_basic__slm_writes__read,
                .max_uint64 = acmgt1__compute_basic__slm_writes__max,
                .group = "L1Cache",
            },

            {
                .name = "XMX Pipe Active",
                .symbol_name = "XmxActive",
                .desc = "The percentage of time in which XVE XMX pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE AVG IPC Rate",
                .symbol_name = "XveAvgIpcRate",
                .desc = "The average rate of IPC calculated for 2 FPU pipelines.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NUMBER,
                .read_float = acmgt1__compute_basic__xve_avg_ipc_rate__read,
                .max_float = acmgt1__compute_basic__xve_avg_ipc_rate__max,
                .group = "VectorEngine",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT16 Instruction",
                .symbol_name = "XveFpuFlt16",
                .desc = "The percentage of time in which FLT16 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_fpu_flt16__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT32 Instruction",
                .symbol_name = "XveFpuFlt32",
                .desc = "The percentage of time in which FLT32 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_fpu_flt32__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FPU FLT64 Instruction",
                .symbol_name = "XveFpuFlt64",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_fpu_flt64__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XMX And FPU Pipes Active",
                .symbol_name = "XveFpuXmxActive",
                .desc = "The percentage of time in which XVE XMX and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_fpu_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 25);
}


static void
acmgt1_add_threads_and_rast1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadsAndRast1";
    metric_set->symbol_name = "ThreadsAndRast1";
    metric_set->hw_config_guid = "952f5f55-449d-43db-87d7-6113e9c3b89a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_threads_and_rast1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__threads_and_rast1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__threads_and_rast1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "Number of DS thread dispatches",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__threads_and_rast1__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__threads_and_rast1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__threads_and_rast1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "Number of HS thread dispatches",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__threads_and_rast1__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "Number of VS thread dispatches",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__threads_and_rast1__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}


static void
acmgt1_add_threads_and_rast2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadsAndRast2";
    metric_set->symbol_name = "ThreadsAndRast2";
    metric_set->hw_config_guid = "797ae4a3-6d36-4be1-9064-a9bc3263957f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_threads_and_rast2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__threads_and_rast2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__threads_and_rast2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__threads_and_rast2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__threads_and_rast2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "Number of PS thread dispatches",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__threads_and_rast2__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt1_add_threads_and_rast3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadsAndRast3";
    metric_set->symbol_name = "ThreadsAndRast3";
    metric_set->hw_config_guid = "abb4b8fd-b9cd-4b11-a610-1c0707af14cf";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_threads_and_rast3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__threads_and_rast3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__threads_and_rast3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__threads_and_rast3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__threads_and_rast3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "Number of GS thread dispatches",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__threads_and_rast3__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "Early Hi-Depth Test Fails",
                .symbol_name = "HiDepthTestFails",
                .desc = "The total number of pixels dropped on early hierarchical depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt1__threads_and_rast3__hi_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}


static void
acmgt1_add_threads_and_rast4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ThreadsAndRast4";
    metric_set->symbol_name = "ThreadsAndRast4";
    metric_set->hw_config_guid = "2da159d5-8ace-42bb-9d81-26f2b162d8d8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_threads_and_rast4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__threads_and_rast4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__threads_and_rast4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "Early Depth Test Fails",
                .symbol_name = "EarlyDepthTestFails",
                .desc = "The total number of pixels dropped on early depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__threads_and_rast4__early_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__threads_and_rast4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__threads_and_rast4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt1_add_async_compute_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AsyncCompute";
    metric_set->symbol_name = "AsyncCompute";
    metric_set->hw_config_guid = "91273130-42fe-4c5e-ba34-6f9140b612c6";
    metric_set->counters = calloc(18, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_async_compute_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC CS EM Pipe Active",
                .symbol_name = "AsyncCsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__async_cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "ASYNC CS FPU Pipe Active",
                .symbol_name = "AsyncCsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__async_cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__async_compute__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__async_compute__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS EM Pipe Active",
                .symbol_name = "CsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS FPU Pipe Active",
                .symbol_name = "CsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__async_compute__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__async_compute__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__async_compute__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__async_compute__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 18);
}


static void
acmgt1_add_xve_activity1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "XveActivity1";
    metric_set->symbol_name = "XveActivity1";
    metric_set->hw_config_guid = "fd9d1ad4-13b3-4583-9f2c-998f627e370d";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_xve_activity1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__xve_activity1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__xve_activity1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Send Pipe Active",
                .symbol_name = "CsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__cs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__xve_activity1__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "DS EM Pipe Active",
                .symbol_name = "DsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__ds_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS FPU Pipe Active",
                .symbol_name = "DsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__ds_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "DS Send Pipe Active",
                .symbol_name = "DsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__ds_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__xve_activity1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__xve_activity1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS EM Pipe Active",
                .symbol_name = "GsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__gs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS FPU Pipe Active",
                .symbol_name = "GsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__gs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "GS Send Pipe Active",
                .symbol_name = "GsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__gs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS EM Pipe Active",
                .symbol_name = "HsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__hs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS FPU Pipe Active",
                .symbol_name = "HsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__hs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "HS Send Pipe Active",
                .symbol_name = "HsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__xve_activity1__hs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}


static void
acmgt1_add_gpu_busyness_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "GpuBusyness";
    metric_set->symbol_name = "GpuBusyness";
    metric_set->hw_config_guid = "4b785529-8efb-471e-93c5-481dae7b3b8b";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_gpu_busyness_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "Any compute engine busy",
                .symbol_name = "AnyComputeEngineBusy",
                .desc = "The percentage of time when any compute engine is busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__any_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__gpu_busyness__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__gpu_busyness__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "Blitter Ring Busy",
                .symbol_name = "BlitterBusy",
                .desc = "The percentage of time when blitter command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__blitter_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine0 Ring Busy",
                .symbol_name = "ComputeEngine0Busy",
                .desc = "The percentage of time when compute command streamer 0 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__compute_engine0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine1 Ring Busy",
                .symbol_name = "ComputeEngine1Busy",
                .desc = "The percentage of time when compute command streamer 1 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__compute_engine1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine2 Ring Busy",
                .symbol_name = "ComputeEngine2Busy",
                .desc = "The percentage of time when compute command streamer 2 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__compute_engine2_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "ComputeEngine3 Ring Busy",
                .symbol_name = "ComputeEngine3Busy",
                .desc = "The percentage of time when compute command streamer 3 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__compute_engine3_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__gpu_busyness__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__gpu_busyness__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__gpu_busyness__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Render and any compute engines are simultaneously busy",
                .symbol_name = "RenderAndAnyComputeEngineBusy",
                .desc = "The percentage of time when render and any compute engines are simultaneously busy",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__render_and_any_compute_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "Render Ring Busy",
                .symbol_name = "RenderBusy",
                .desc = "The percentage of time when render command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__render_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "Vdbox00 Ring Busy",
                .symbol_name = "Vdbox00Busy",
                .desc = "The percentage of time when vdbox00 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__vdbox00_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vdbox10 Ring Busy",
                .symbol_name = "Vdbox10Busy",
                .desc = "The percentage of time when vdbox10 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__vdbox10_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vebox0 Ring Busy",
                .symbol_name = "Vebox0Busy",
                .desc = "The percentage of time when vebox0 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__vebox0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "Vebox1 Ring Busy",
                .symbol_name = "Vebox1Busy",
                .desc = "The percentage of time when vebox1 command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__vebox1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Media",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__gpu_busyness__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt1_add_render_pipe_profile1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile1";
    metric_set->hw_config_guid = "8a0c5d31-e0cb-4d2c-8056-f3824c57ad9a";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_render_pipe_profile1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__render_pipe_profile1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__render_pipe_profile1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC20 Bottleneck",
                .symbol_name = "Bc20Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__bc20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper2 Bottleneck",
                .symbol_name = "Cl2Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__cl2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL2 Stall",
                .symbol_name = "Cl2Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__cl2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS2 Bottleneck",
                .symbol_name = "Ds2Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__ds2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS2 Stall",
                .symbol_name = "Ds2Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__ds2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__render_pipe_profile1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__render_pipe_profile1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS2 Bottleneck",
                .symbol_name = "Gs2Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__gs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth20 Bottleneck",
                .symbol_name = "HiDepth20Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__hi_depth20_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS2 Bottleneck",
                .symbol_name = "Hs2Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__hs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS2 Stall",
                .symbol_name = "Hs2Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__hs2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF2 Bottleneck",
                .symbol_name = "Sf2Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__sf2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF2 Stall",
                .symbol_name = "Sf2Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__sf2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO2 Bottleneck",
                .symbol_name = "So2Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__so2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO2 Stall",
                .symbol_name = "So2Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__so2_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF2 Bottleneck",
                .symbol_name = "Vf2Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__vf2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS2 Bottleneck",
                .symbol_name = "Vs2Bottleneck",
                .desc = "The percentage of time in which VS2 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile1__vs2_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt1_add_render_pipe_profile2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile2";
    metric_set->hw_config_guid = "0f40fba0-129a-4a19-87de-5fdbe111b915";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_render_pipe_profile2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__render_pipe_profile2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__render_pipe_profile2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC30 Bottleneck",
                .symbol_name = "Bc30Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__bc30_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Clipper3 Bottleneck",
                .symbol_name = "Cl3Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__cl3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "CL3 Stall",
                .symbol_name = "Cl3Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__cl3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS3 Bottleneck",
                .symbol_name = "Ds3Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__ds3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "DS3 Stall",
                .symbol_name = "Ds3Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__ds3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__render_pipe_profile2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__render_pipe_profile2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS3 Bottleneck",
                .symbol_name = "Gs3Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__gs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Hi-Depth30 Bottleneck",
                .symbol_name = "HiDepth30Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__hi_depth30_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "HS3 Bottleneck",
                .symbol_name = "Hs3Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__hs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "HS3 Stall",
                .symbol_name = "Hs3Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__hs3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF3 Bottleneck",
                .symbol_name = "Sf3Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__sf3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SF3 Stall",
                .symbol_name = "Sf3Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__sf3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO3 Bottleneck",
                .symbol_name = "So3Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__so3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "SO3 Stall",
                .symbol_name = "So3Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__so3_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VF3 Bottleneck",
                .symbol_name = "Vf3Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__vf3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "VS3 Bottleneck",
                .symbol_name = "Vs3Bottleneck",
                .desc = "The percentage of time in which VS3 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__render_pipe_profile2__vs3_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt1_add_l3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3";
    metric_set->symbol_name = "L3";
    metric_set->hw_config_guid = "24695fb7-a404-4cd6-9aad-d23738b6d499";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_l3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__l3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__l3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__l3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__l3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Quad1 L3 Bank0 Input Available",
                .symbol_name = "L31Bank0InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank0 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank0 Output Ready",
                .symbol_name = "L31Bank0OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank0 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank1 Input Available",
                .symbol_name = "L31Bank1InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank1 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank1 Output Ready",
                .symbol_name = "L31Bank1OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank1 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank2 Input Available",
                .symbol_name = "L31Bank2InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank2 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank2 Output Ready",
                .symbol_name = "L31Bank2OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank2 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank3 Input Available",
                .symbol_name = "L31Bank3InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank3 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank3 Output Ready",
                .symbol_name = "L31Bank3OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank3 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank4 Input Available",
                .symbol_name = "L31Bank4InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank4 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank4_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank4 Output Ready",
                .symbol_name = "L31Bank4OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank4 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank4_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank5 Input Available",
                .symbol_name = "L31Bank5InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank5 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank5_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank5 Output Ready",
                .symbol_name = "L31Bank5OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank5 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank5_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank6 Input Available",
                .symbol_name = "L31Bank6InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank6 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank6_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank6 Output Ready",
                .symbol_name = "L31Bank6OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank6 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank6_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank7 Input Available",
                .symbol_name = "L31Bank7InputAvailable",
                .desc = "The percentage of time in which Quad1 L3 bank7 has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank7_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },

            {
                .name = "Quad1 L3 Bank7 Output Ready",
                .symbol_name = "L31Bank7OutputReady",
                .desc = "The percentage of time in which quad1 L3 bank7 output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l3__l31_bank7_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt1_sampler_Sampler20InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler20OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler21InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler21OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler22InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler22OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler23InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler23OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler30InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler30OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler31InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler31OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler32InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler32OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler33InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_sampler_Sampler33OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_sampler_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_Slice23";
    metric_set->symbol_name = "Sampler";
    metric_set->hw_config_guid = "4486113b-a8a7-4f75-a1c2-7d307fa0e00e";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_sampler_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__sampler__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__sampler__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__sampler__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__sampler__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice2 Xe Core0 Input Available",
                .symbol_name = "Sampler20InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler20_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler20InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler20OutputReady",
                .desc = "The percentage of time in which slice2 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler20_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler20OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core1 Input Available",
                .symbol_name = "Sampler21InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler21_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler21InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler21OutputReady",
                .desc = "The percentage of time in which slice2 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler21_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler21OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core2 Input Available",
                .symbol_name = "Sampler22InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler22_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler22InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler22OutputReady",
                .desc = "The percentage of time in which slice2 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler22_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler22OutputReady_availability,
            },

            {
                .name = "Slice2 Xe Core3 Input Available",
                .symbol_name = "Sampler23InputAvailable",
                .desc = "The percentage of time in which slice2 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler23_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler23InputAvailable_availability,
            },

            {
                .name = "Slice2 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler23OutputReady",
                .desc = "The percentage of time in which slice2 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler23_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler23OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core0 Input Available",
                .symbol_name = "Sampler30InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler30_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler30InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler30OutputReady",
                .desc = "The percentage of time in which slice3 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler30_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler30OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core1 Input Available",
                .symbol_name = "Sampler31InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler31_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler31InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler31OutputReady",
                .desc = "The percentage of time in which slice3 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler31_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler31OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core2 Input Available",
                .symbol_name = "Sampler32InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler32_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler32InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler32OutputReady",
                .desc = "The percentage of time in which slice3 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler32_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler32OutputReady_availability,
            },

            {
                .name = "Slice3 Xe Core3 Input Available",
                .symbol_name = "Sampler33InputAvailable",
                .desc = "The percentage of time in which slice3 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler33_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler33InputAvailable_availability,
            },

            {
                .name = "Slice3 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler33OutputReady",
                .desc = "The percentage of time in which slice3 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__sampler__sampler33_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_sampler_Sampler33OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt1_hdc_and_sf1_NonSamplerShader20AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_hdc_and_sf1_NonSamplerShader21AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_hdc_and_sf1_NonSamplerShader22AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_hdc_and_sf1_NonSamplerShader23AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_hdc_and_sf1_NonSamplerShader30AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_hdc_and_sf1_NonSamplerShader31AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_hdc_and_sf1_NonSamplerShader32AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_hdc_and_sf1_NonSamplerShader33AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_hdc_and_sf1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF1";
    metric_set->symbol_name = "HDCAndSF1";
    metric_set->hw_config_guid = "75fc20f8-8694-47f2-b67b-cbb35f697a8e";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_hdc_and_sf1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__hdc_and_sf1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__hdc_and_sf1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__hdc_and_sf1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__hdc_and_sf1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice2 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader20AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader20_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader20AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader21AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader21_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader21AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader22AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader22_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader22AccessStalledOnL3_availability,
            },

            {
                .name = "Slice2 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader23AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice2 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader23_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader23AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader30AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader30_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader30AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader31AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader31_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader31AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader32AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader32_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader32AccessStalledOnL3_availability,
            },

            {
                .name = "Slice3 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader33AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice3 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf1__non_sampler_shader33_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_hdc_and_sf1_NonSamplerShader33AccessStalledOnL3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}


static void
acmgt1_add_hdc_and_sf2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF2";
    metric_set->symbol_name = "HDCAndSF2";
    metric_set->hw_config_guid = "d5e02a31-fc87-4cdc-8136-4b19e00b7e94";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_hdc_and_sf2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__hdc_and_sf2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__hdc_and_sf2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "SQ20 is full",
                .symbol_name = "GTRequestQueue20Full",
                .desc = "The percentage of time when IDI0 SQ20 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf2__gt_request_queue20_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "SQ30 is full",
                .symbol_name = "GTRequestQueue30Full",
                .desc = "The percentage of time when IDI0 SQ30 is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf2__gt_request_queue30_full__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__hdc_and_sf2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__hdc_and_sf2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Polygon (Slice2) Data Ready",
                .symbol_name = "Poly2DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf2__poly2_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },

            {
                .name = "Polygon (Slice3) Data Ready",
                .symbol_name = "Poly3DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__hdc_and_sf2__poly3_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt1_rasterizer_and_pixel_backend1_Rasterizer2InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_rasterizer_and_pixel_backend1_Rasterizer3OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_rasterizer_and_pixel_backend1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend1";
    metric_set->symbol_name = "RasterizerAndPixelBackend1";
    metric_set->hw_config_guid = "08858210-0dc3-452b-afee-e5c7811c01cb";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_rasterizer_and_pixel_backend1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__rasterizer_and_pixel_backend1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__rasterizer_and_pixel_backend1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS10 Output Available",
                .symbol_name = "PSOutput10Available",
                .desc = "The percentage of time in which PS10 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__ps_output10_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "PS11 Output Available",
                .symbol_name = "PSOutput11Available",
                .desc = "The percentage of time in which PS11 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__ps_output11_available__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Slice2 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData20Ready",
                .desc = "The percentage of time in which slice2  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__pixel_data20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice2 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData21Ready",
                .desc = "The percentage of time in which slice2  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__pixel_data21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Pixel Values 10 Ready",
                .symbol_name = "PixelValues10Ready",
                .desc = "The percentage of time in which pixel values 10 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__pixel_values10_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Pixel Values 11 Ready",
                .symbol_name = "PixelValues11Ready",
                .desc = "The percentage of time in which pixel values 11 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__pixel_values11_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
            },

            {
                .name = "Slice2 Rasterizer Input Available",
                .symbol_name = "Rasterizer2InputAvailable",
                .desc = "The percentage of time in which slice2 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__rasterizer2_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_rasterizer_and_pixel_backend1_Rasterizer2InputAvailable_availability,
            },

            {
                .name = "Slice3 Rasterizer Output Ready",
                .symbol_name = "Rasterizer3OutputReady",
                .desc = "The percentage of time in which slice3 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend1__rasterizer3_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_rasterizer_and_pixel_backend1_Rasterizer3OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt1_rasterizer_and_pixel_backend2_Rasterizer2OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_rasterizer_and_pixel_backend2_Rasterizer3InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_rasterizer_and_pixel_backend2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend2";
    metric_set->symbol_name = "RasterizerAndPixelBackend2";
    metric_set->hw_config_guid = "30b71e0c-55eb-49ed-8863-ee7db68ff1b1";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_rasterizer_and_pixel_backend2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__rasterizer_and_pixel_backend2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__rasterizer_and_pixel_backend2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice3 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData30Ready",
                .desc = "The percentage of time in which slice3  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend2__pixel_data30_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice3 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData31Ready",
                .desc = "The percentage of time in which slice3  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend2__pixel_data31_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
            },

            {
                .name = "Slice2 Rasterizer Output Ready",
                .symbol_name = "Rasterizer2OutputReady",
                .desc = "The percentage of time in which slice2 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend2__rasterizer2_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_rasterizer_and_pixel_backend2_Rasterizer2OutputReady_availability,
            },

            {
                .name = "Slice3 Rasterizer Input Available",
                .symbol_name = "Rasterizer3InputAvailable",
                .desc = "The percentage of time in which slice3 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__rasterizer_and_pixel_backend2__rasterizer3_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_rasterizer_and_pixel_backend2_Rasterizer3InputAvailable_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt1_tdl1_NonPSThread20ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_NonPSThread21ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_NonPSThread22ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_NonPSThread23ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_NonPSThread30ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_NonPSThread31ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_NonPSThread32ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_NonPSThread33ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader23ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader23ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader23ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader23ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader33ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader33ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader33ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl1_ThreadHeader33ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_tdl1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL1";
    metric_set->symbol_name = "TDL1";
    metric_set->hw_config_guid = "3620f0df-42c6-4904-b395-5497f5a2ea4b";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_tdl1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__tdl1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__tdl1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__tdl1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__tdl1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread20ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread20_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread20ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread21ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread21_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread21ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread22ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread22_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread22ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread23ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread23_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread23ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread30ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread30_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread30ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread31ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread31_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread31ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread32ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread32_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread32ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread33ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__non_ps_thread33_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_NonPSThread33ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader23ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header23_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader23ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader23ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header23_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader23ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader23ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header23_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader23ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader23ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header23_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader23ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader33ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header33_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader33ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader33ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header33_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader33ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader33ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header33_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader33ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader33ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl1__thread_header33_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl1_ThreadHeader33ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt1_tdl2_PSThread20ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl2_PSThread21ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl2_PSThread22ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl2_PSThread23ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl2_PSThread30ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl2_PSThread31ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl2_PSThread32ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl2_PSThread33ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_tdl2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL2";
    metric_set->symbol_name = "TDL2";
    metric_set->hw_config_guid = "28357a3a-a53b-4da4-a5b7-395dbfa501f1";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_tdl2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__tdl2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__tdl2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__tdl2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__tdl2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread20ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread20_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread20ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread21ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread21_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread21ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread22ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread22_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread22ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread23ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread23_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread23ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread30ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread30_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread30ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread31ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread31_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread31ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread32ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread32_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread32ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread33ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl2__ps_thread33_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl2_PSThread33ReadyForDispatch_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt1_tdl3_ThreadHeader20Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader20ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader20ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader20ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader20ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader21Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader21ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader21ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader21ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader21ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader22Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader22ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader22ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader22ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader22ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl3_ThreadHeader23Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_tdl3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL3";
    metric_set->symbol_name = "TDL3";
    metric_set->hw_config_guid = "262cf8cb-824e-4f48-bac4-6be3d8dda6a5";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_tdl3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__tdl3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__tdl3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__tdl3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__tdl3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader20Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header20_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader20Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader20ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header20_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader20ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader20ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header20_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader20ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader20ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header20_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader20ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader20ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header20_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader20ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader21Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header21_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader21Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader21ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header21_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader21ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader21ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header21_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader21ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader21ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header21_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader21ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader21ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header21_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader21ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader22Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header22_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader22Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader22ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header22_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader22ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader22ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header22_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader22ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader22ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header22_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader22ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader22ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header22_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader22ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice2 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader23Ready",
                .desc = "The percentage of time in which thread header is ready on slice2 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl3__thread_header23_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl3_ThreadHeader23Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool acmgt1_tdl4_ThreadHeader30Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader30ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader30ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader30ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader30ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader31Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader31ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader31ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader31ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader31ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader32Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader32ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader32ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader32ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader32ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_tdl4_ThreadHeader33Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_tdl4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL4";
    metric_set->symbol_name = "TDL4";
    metric_set->hw_config_guid = "1e629e21-abd2-418e-a184-753977bb529b";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_tdl4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__tdl4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__tdl4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__tdl4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__tdl4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader30Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header30_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader30Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader30ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header30_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader30ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader30ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header30_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader30ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader30ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header30_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader30ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader30ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header30_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader30ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader31Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header31_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader31Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader31ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header31_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader31ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader31ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header31_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader31ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader31ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header31_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader31ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader31ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header31_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader31ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader32Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header32_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader32Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader32ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header32_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader32ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader32ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header32_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader32ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader32ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header32_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader32ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader32ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header32_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader32ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice3 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader33Ready",
                .desc = "The percentage of time in which thread header is ready on slice3 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__tdl4__thread_header33_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_tdl4_ThreadHeader33Ready_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
acmgt1_add_test_oa_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set TestOa";
    metric_set->symbol_name = "TestOa";
    metric_set->hw_config_guid = "57f210de-b537-464a-af7b-7dfe2f3780c1";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_test_oa_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__test_oa__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__test_oa__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "TestCounter0",
                .symbol_name = "Counter0",
                .desc = "HW test counter 0. Factor: 0.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter1",
                .symbol_name = "Counter1",
                .desc = "HW test counter 1. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter2",
                .symbol_name = "Counter2",
                .desc = "HW test counter 2. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter3",
                .symbol_name = "Counter3",
                .desc = "HW test counter 3. Factor: 0.5",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter4",
                .symbol_name = "Counter4",
                .desc = "HW test counter 4. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter5",
                .symbol_name = "Counter5",
                .desc = "HW test counter 5. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter6",
                .symbol_name = "Counter6",
                .desc = "HW test counter 6. Factor: 0.16666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter7",
                .symbol_name = "Counter7",
                .desc = "HW test counter 7. Factor: 0.6666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter8",
                .symbol_name = "Counter8",
                .desc = "HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter9 - OAR enable",
                .symbol_name = "Counter9",
                .desc = "HW test counter 9. Should be equal to 1 in query.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__test_oa__counter9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__test_oa__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__test_oa__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}


static void
acmgt1_add_compute_overview_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "ComputeOverview";
    metric_set->symbol_name = "ComputeOverview";
    metric_set->hw_config_guid = "37b5b93b-6acf-4726-9b57-1a65fab22bb2";
    metric_set->counters = calloc(26, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_compute_overview_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__compute_overview__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__compute_overview__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__compute_overview__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__compute_overview__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__compute_overview__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__compute_overview__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__compute_overview__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__compute_overview__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BYTE READ",
                .symbol_name = "L3_BYTE_READ",
                .desc = "Number of bytes read from L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__compute_overview__l3_byte_read__read,
                .max_uint64 = acmgt1__compute_overview__l3_byte_read__max,
                .group = "L3Cache",
            },

            {
                .name = "L3 BYTE WRITE",
                .symbol_name = "L3_BYTE_WRITE",
                .desc = "Number of bytes written to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__compute_overview__l3_byte_write__read,
                .max_uint64 = acmgt1__compute_overview__l3_byte_write__max,
                .group = "L3Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE ATOMIC ACCESS COUNT",
                .symbol_name = "XVE_ATOMIC_ACCESS_COUNT",
                .desc = "Number of shader atomic memory accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__compute_overview__xve_atomic_access_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BARRIER MESSAGE COUNT",
                .symbol_name = "XVE_BARRIER_MESSAGE_COUNT",
                .desc = "Number of shader barrier messages",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = acmgt1__compute_overview__xve_barrier_message_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__compute_overview__xve_busy__read,
                .max_uint64 = acmgt1__compute_overview__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE COMPUTE THREAD COUNT",
                .symbol_name = "XVE_COMPUTE_THREAD_COUNT",
                .desc = "Number of compute shader hardware threads dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__compute_overview__xve_compute_thread_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__compute_overview__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt1__compute_overview__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__compute_overview__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt1__compute_overview__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL",
                .desc = "Number of instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__compute_overview__xve_inst_executed_control_all__read,
                .max_uint64 = acmgt1__compute_overview__xve_inst_executed_control_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_inst_executed_control_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__compute_overview__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt1__compute_overview__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__compute_overview__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt1__compute_overview__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE",
                .desc = "Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_pipe_alu0_and_alu1_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE",
                .desc = "Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_pipe_alu0_and_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__compute_overview__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 26);
}


static void
acmgt1_add_l1_profile_reads__xe_core0_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileReads";
    metric_set->symbol_name = "L1ProfileReads_XeCore0";
    metric_set->hw_config_guid = "a2fe4388-0540-4550-b57e-6948cd7ab47a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_l1_profile_reads__xe_core0_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core0__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core0__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core0__load_store_cache_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE READ",
                .symbol_name = "SLM_BYTE_READ",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__slm_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core0__slm_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_reads__xe_core0__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core0__xve_busy__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core0__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_reads__xe_core0__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_reads__xe_core0__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt1_add_l1_profile_reads__xe_core3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileReads";
    metric_set->symbol_name = "L1ProfileReads_XeCore3";
    metric_set->hw_config_guid = "16bc63c3-d365-4bee-baf7-bafbc1aa7c2d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_l1_profile_reads__xe_core3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core3__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core3__load_store_cache_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE READ",
                .symbol_name = "SLM_BYTE_READ",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__slm_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core3__slm_byte_read__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_reads__xe_core3__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_reads__xe_core3__xve_busy__read,
                .max_uint64 = acmgt1__l1_profile_reads__xe_core3__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_reads__xe_core3__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_reads__xe_core3__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt1_add_l1_profile_slm_bank_conflicts__xe_core0_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileSlmBankConflicts";
    metric_set->symbol_name = "L1ProfileSlmBankConflicts_XeCore0";
    metric_set->hw_config_guid = "28da4c17-4629-4111-a575-787a85100db9";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_l1_profile_slm_bank_conflicts__xe_core0_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__slm_bank_conflict_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_slm_bank_conflicts__xe_core0__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
acmgt1_add_l1_profile_slm_bank_conflicts__xe_core3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileSlmBankConflicts";
    metric_set->symbol_name = "L1ProfileSlmBankConflicts_XeCore3";
    metric_set->hw_config_guid = "825f82b5-486a-4ca2-96fa-f358871984b0";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_l1_profile_slm_bank_conflicts__xe_core3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__slm_bank_conflict_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__read,
                .max_uint64 = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_slm_bank_conflicts__xe_core3__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
acmgt1_add_l1_profile_writes__xe_core0_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileWrites";
    metric_set->symbol_name = "L1ProfileWrites_XeCore0";
    metric_set->hw_config_guid = "5d58094c-105e-4562-b53d-68185319c794";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_l1_profile_writes__xe_core0_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core0__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core0__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core0__load_store_cache_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE WRITE",
                .symbol_name = "SLM_BYTE_WRITE",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__slm_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core0__slm_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_writes__xe_core0__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core0__xve_busy__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core0__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_writes__xe_core0__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_writes__xe_core0__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt1_add_l1_profile_writes__xe_core3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L1ProfileWrites";
    metric_set->symbol_name = "L1ProfileWrites_XeCore3";
    metric_set->hw_config_guid = "3ce21cd6-fe3e-468f-ae53-07dbf73c45f9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_l1_profile_writes__xe_core3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core3__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__load_store_cache_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core3__load_store_cache_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "SLM BYTE WRITE",
                .symbol_name = "SLM_BYTE_WRITE",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__slm_byte_write__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core3__slm_byte_write__max,
                .group = "L1Cache",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_writes__xe_core3__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__l1_profile_writes__xe_core3__xve_busy__read,
                .max_uint64 = acmgt1__l1_profile_writes__xe_core3__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_writes__xe_core3__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__l1_profile_writes__xe_core3__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
acmgt1_add_dataport_reads_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DataportReads";
    metric_set->symbol_name = "DataportReads";
    metric_set->hw_config_guid = "54d0193f-f8e0-4b81-99ba-e73a23fd9418";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_dataport_reads_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__dataport_reads__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__dataport_reads__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ",
                .symbol_name = "DATAPORT_BYTE_READ",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_reads__dataport_byte_read__read,
                .max_uint64 = acmgt1__dataport_reads__dataport_byte_read__max,
                .group = "Dataport",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_reads__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__dataport_reads__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_reads__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__dataport_reads__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__dataport_reads__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__dataport_reads__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HOST TO GPUMEM BYTE READ",
                .symbol_name = "HOST_TO_GPUMEM_BYTE_READ",
                .desc = "Number of bytes read by host from GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_reads__host_to_gpumem_byte_read__read,
                .max_uint64 = acmgt1__dataport_reads__host_to_gpumem_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "HOST TO GPUMEM BYTE WRITE",
                .symbol_name = "HOST_TO_GPUMEM_BYTE_WRITE",
                .desc = "Number of bytes written by host to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_reads__host_to_gpumem_byte_write__read,
                .max_uint64 = acmgt1__dataport_reads__host_to_gpumem_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__dataport_reads__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__dataport_reads__xve_busy__read,
                .max_uint64 = acmgt1__dataport_reads__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE COMPUTE THREAD COUNT",
                .symbol_name = "XVE_COMPUTE_THREAD_COUNT",
                .desc = "Number of compute shader hardware threads dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__dataport_reads__xve_compute_thread_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__dataport_reads__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__dataport_reads__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}


static void
acmgt1_add_dataport_writes_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "DataportWrites";
    metric_set->symbol_name = "DataportWrites";
    metric_set->hw_config_guid = "17982512-46b0-4b58-9e8d-d59b5bf8b3f5";
    metric_set->counters = calloc(14, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_dataport_writes_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__dataport_writes__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__dataport_writes__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE WRITE",
                .symbol_name = "DATAPORT_BYTE_WRITE",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_writes__dataport_byte_write__read,
                .max_uint64 = acmgt1__dataport_writes__dataport_byte_write__max,
                .group = "Dataport",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_writes__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__dataport_writes__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_writes__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__dataport_writes__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__dataport_writes__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__dataport_writes__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 READ",
                .symbol_name = "SAMPLER_L3_READ",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__dataport_writes__sampler_l3_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "SYSMEM BYTE READ",
                .symbol_name = "SYSMEM_BYTE_READ",
                .desc = "Number of system memory bytes read (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_writes__sysmem_byte_read__read,
                .max_uint64 = acmgt1__dataport_writes__sysmem_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "SYSMEM BYTE WRITE",
                .symbol_name = "SYSMEM_BYTE_WRITE",
                .desc = "Number of system memory bytes written (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__dataport_writes__sysmem_byte_write__read,
                .max_uint64 = acmgt1__dataport_writes__sysmem_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__dataport_writes__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE BUSY",
                .symbol_name = "XVE_BUSY",
                .desc = "Any XVE thread loaded.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__dataport_writes__xve_busy__read,
                .max_uint64 = acmgt1__dataport_writes__xve_busy__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE COMPUTE THREAD COUNT",
                .symbol_name = "XVE_COMPUTE_THREAD_COUNT",
                .desc = "Number of compute shader hardware threads dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = acmgt1__dataport_writes__xve_compute_thread_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__dataport_writes__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__dataport_writes__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 14);
}


static void
acmgt1_add_ext1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1";
    metric_set->symbol_name = "Ext1";
    metric_set->hw_config_guid = "480895b0-8013-4be1-8bbf-fc3f1ad2e97f";
    metric_set->counters = calloc(25, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI0",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI0",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1__gpu_memory_active_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI1",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI1",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1__gpu_memory_active_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ",
                .symbol_name = "GPU_MEMORY_BYTE_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext1__gpu_memory_byte_read__read,
                .max_uint64 = acmgt1__ext1__gpu_memory_byte_read__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt1__ext1__gpu_memory_byte_read_bw__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt1__ext1__gpu_memory_byte_read_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt1__ext1__gpu_memory_byte_read_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext1__gpu_memory_byte_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext1__gpu_memory_byte_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext1__gpu_memory_byte_write__read,
                .max_uint64 = acmgt1__ext1__gpu_memory_byte_write__max,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt1__ext1__gpu_memory_byte_write_bw__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt1__ext1__gpu_memory_byte_write_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = acmgt1__ext1__gpu_memory_byte_write_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext1__gpu_memory_byte_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext1__gpu_memory_byte_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ",
                .symbol_name = "GPU_MEMORY_READ",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__gpu_memory_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI0",
                .symbol_name = "GPU_MEMORY_READ_SQIDI0",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__gpu_memory_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY READ SQIDI1",
                .symbol_name = "GPU_MEMORY_READ_SQIDI1",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__gpu_memory_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE",
                .symbol_name = "GPU_MEMORY_WRITE",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__gpu_memory_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__gpu_memory_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__gpu_memory_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SYSMEM TRANSACTION READ",
                .symbol_name = "SYSMEM_TRANSACTION_READ",
                .desc = "Number of system memory reads (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__sysmem_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "SYSMEM TRANSACTION WRITE",
                .symbol_name = "SYSMEM_TRANSACTION_WRITE",
                .desc = "Number of system memory writes (upstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1__sysmem_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 25);
}


static void
acmgt1_add_ext2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext2";
    metric_set->symbol_name = "Ext2";
    metric_set->hw_config_guid = "b899d843-d8ce-4803-8174-f2bf1107de00";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext2__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext2__gpu_memory_32_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext2__gpu_memory_64_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI0",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI0",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext2__gpu_memory_request_queue_full_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI1",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI1",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext2__gpu_memory_request_queue_full_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}


static void
acmgt1_add_ext3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext3";
    metric_set->symbol_name = "Ext3";
    metric_set->hw_config_guid = "59e0ed29-cd2d-43ee-bf49-e4637e8ef9ee";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext3__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext3__gpu_memory_32_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext3__gpu_memory_32_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext3__gpu_memory_64_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext3__gpu_memory_64_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HOST TO GPUMEM TRANSACTION READ",
                .symbol_name = "HOST_TO_GPUMEM_TRANSACTION_READ",
                .desc = "Number of host reads to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext3__host_to_gpumem_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "HOST TO GPUMEM TRANSACTION WRITE",
                .symbol_name = "HOST_TO_GPUMEM_TRANSACTION_WRITE",
                .desc = "Number of host writes to GPU local (HBM) memory (downstream)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext3__host_to_gpumem_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt1_ext4_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext4_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext4";
    metric_set->symbol_name = "Ext4";
    metric_set->hw_config_guid = "475c650e-1045-45dc-a280-3365f7af8f8c";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext4__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 READ L3BANK0",
                .symbol_name = "L3_READ_L3BANK0",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK0_availability,
            },

            {
                .name = "L3 READ L3BANK1",
                .symbol_name = "L3_READ_L3BANK1",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK1_availability,
            },

            {
                .name = "L3 READ L3BANK2",
                .symbol_name = "L3_READ_L3BANK2",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK2_availability,
            },

            {
                .name = "L3 READ L3BANK3",
                .symbol_name = "L3_READ_L3BANK3",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK3_availability,
            },

            {
                .name = "L3 READ L3BANK4",
                .symbol_name = "L3_READ_L3BANK4",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK4_availability,
            },

            {
                .name = "L3 READ L3BANK5",
                .symbol_name = "L3_READ_L3BANK5",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK5_availability,
            },

            {
                .name = "L3 READ L3BANK6",
                .symbol_name = "L3_READ_L3BANK6",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK6_availability,
            },

            {
                .name = "L3 READ L3BANK7",
                .symbol_name = "L3_READ_L3BANK7",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_READ_L3BANK7_availability,
            },

            {
                .name = "L3 WRITE L3BANK0",
                .symbol_name = "L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "L3 WRITE L3BANK1",
                .symbol_name = "L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "L3 WRITE L3BANK2",
                .symbol_name = "L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "L3 WRITE L3BANK3",
                .symbol_name = "L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "L3 WRITE L3BANK4",
                .symbol_name = "L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "L3 WRITE L3BANK5",
                .symbol_name = "L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "L3 WRITE L3BANK6",
                .symbol_name = "L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "L3 WRITE L3BANK7",
                .symbol_name = "L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext4__l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext4_L3_WRITE_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext5";
    metric_set->symbol_name = "Ext5";
    metric_set->hw_config_guid = "b7d7a874-19d8-48e6-bf54-f859a994b0a4";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext5__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 READ L3BANK0",
                .symbol_name = "DATAPORT_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK1",
                .symbol_name = "DATAPORT_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK2",
                .symbol_name = "DATAPORT_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK3",
                .symbol_name = "DATAPORT_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK4",
                .symbol_name = "DATAPORT_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK5",
                .symbol_name = "DATAPORT_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK6",
                .symbol_name = "DATAPORT_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK7",
                .symbol_name = "DATAPORT_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_READ_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK0",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK1",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK2",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK3",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK4",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK5",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK6",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK7",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext5__dataport_l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext5_DATAPORT_L3_WRITE_L3BANK7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
acmgt1_add_ext6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext6";
    metric_set->symbol_name = "Ext6";
    metric_set->hw_config_guid = "f1a94d28-672b-41a6-9ab9-e2040200d28a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext6__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 HIT L3BANK0",
                .symbol_name = "L3_HIT_L3BANK0",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK1",
                .symbol_name = "L3_HIT_L3BANK1",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK2",
                .symbol_name = "L3_HIT_L3BANK2",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK3",
                .symbol_name = "L3_HIT_L3BANK3",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK4",
                .symbol_name = "L3_HIT_L3BANK4",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK5",
                .symbol_name = "L3_HIT_L3BANK5",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK6",
                .symbol_name = "L3_HIT_L3BANK6",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },

            {
                .name = "L3 HIT L3BANK7",
                .symbol_name = "L3_HIT_L3BANK7",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext6__l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext7_SAMPLER_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext7";
    metric_set->symbol_name = "Ext7";
    metric_set->hw_config_guid = "31d119ed-a150-4b52-9206-3f9832e275ea";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext7__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 HIT L3BANK0",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK0",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK1",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK1",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK2",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK2",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK3",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK3",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK4",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK4",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK5",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK5",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK6",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK6",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK7",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK7",
                .desc = "Number of L3 hit requests resulting from sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK0",
                .symbol_name = "SAMPLER_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK1",
                .symbol_name = "SAMPLER_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK2",
                .symbol_name = "SAMPLER_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK3",
                .symbol_name = "SAMPLER_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK4",
                .symbol_name = "SAMPLER_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK5",
                .symbol_name = "SAMPLER_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK6",
                .symbol_name = "SAMPLER_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK7",
                .symbol_name = "SAMPLER_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests resulting from sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext7__sampler_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext7_SAMPLER_L3_READ_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext8_ICACHE_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext8";
    metric_set->symbol_name = "Ext8";
    metric_set->hw_config_guid = "4eb14f16-d2ac-46d3-b974-e413430fddec";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext8__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 HIT L3BANK0",
                .symbol_name = "ICACHE_L3_HIT_L3BANK0",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK1",
                .symbol_name = "ICACHE_L3_HIT_L3BANK1",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK2",
                .symbol_name = "ICACHE_L3_HIT_L3BANK2",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK3",
                .symbol_name = "ICACHE_L3_HIT_L3BANK3",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK4",
                .symbol_name = "ICACHE_L3_HIT_L3BANK4",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK5",
                .symbol_name = "ICACHE_L3_HIT_L3BANK5",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK6",
                .symbol_name = "ICACHE_L3_HIT_L3BANK6",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK7",
                .symbol_name = "ICACHE_L3_HIT_L3BANK7",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK0",
                .symbol_name = "ICACHE_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK1",
                .symbol_name = "ICACHE_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK2",
                .symbol_name = "ICACHE_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK3",
                .symbol_name = "ICACHE_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK4",
                .symbol_name = "ICACHE_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK5",
                .symbol_name = "ICACHE_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK6",
                .symbol_name = "ICACHE_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK7",
                .symbol_name = "ICACHE_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext8__icache_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext8_ICACHE_L3_READ_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext9_SAMPLER_BUSY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext9_SAMPLER_BUSY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext9_SAMPLER_BUSY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext9_SAMPLER_BUSY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext9_SAMPLER_BUSY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext9_SAMPLER_BUSY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext9_SAMPLER_BUSY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext9_SAMPLER_BUSY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext9";
    metric_set->symbol_name = "Ext9";
    metric_set->hw_config_guid = "b875dedd-f121-4f89-b02f-ff2c873e2543";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext9__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER BUSY XECORE0",
                .symbol_name = "SAMPLER_BUSY_XECORE0",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE0_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE1",
                .symbol_name = "SAMPLER_BUSY_XECORE1",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE1_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE2",
                .symbol_name = "SAMPLER_BUSY_XECORE2",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE2_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE3",
                .symbol_name = "SAMPLER_BUSY_XECORE3",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE3_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE4",
                .symbol_name = "SAMPLER_BUSY_XECORE4",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE4_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE5",
                .symbol_name = "SAMPLER_BUSY_XECORE5",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE5_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE6",
                .symbol_name = "SAMPLER_BUSY_XECORE6",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE6_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE7",
                .symbol_name = "SAMPLER_BUSY_XECORE7",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext9__sampler_busy_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext9_SAMPLER_BUSY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_COLOR_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext10_DATAPORT_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext10";
    metric_set->symbol_name = "Ext10";
    metric_set->hw_config_guid = "691b6a0d-d3d7-4b5e-a70e-d8232722cddf";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext10__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR L3 HIT L3BANK0",
                .symbol_name = "COLOR_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK1",
                .symbol_name = "COLOR_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK2",
                .symbol_name = "COLOR_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK3",
                .symbol_name = "COLOR_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK4",
                .symbol_name = "COLOR_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK5",
                .symbol_name = "COLOR_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK6",
                .symbol_name = "COLOR_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK7",
                .symbol_name = "COLOR_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__color_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_COLOR_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK0",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK0",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK1",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK1",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK2",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK2",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK3",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK3",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK4",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK4",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK5",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK5",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK6",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK6",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK7",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK7",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext10__dataport_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext10_DATAPORT_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext11_Z_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext11";
    metric_set->symbol_name = "Ext11";
    metric_set->hw_config_guid = "3c626d93-4368-4115-a21d-8fd8cd10e8fa";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext11__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK0",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK0",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK0_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK1",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK1",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK1_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK2",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK2",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK2_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK3",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK3",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK3_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK4",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK4",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK4_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK5",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK5",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK5_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK6",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK6",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK6_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK7",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK7",
                .desc = "Number of atomic accesses to L3 bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__l3_atomic_access_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_L3_ATOMIC_ACCESS_L3BANK7_availability,
            },

            {
                .name = "Z L3 HIT L3BANK0",
                .symbol_name = "Z_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "Z L3 HIT L3BANK1",
                .symbol_name = "Z_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "Z L3 HIT L3BANK2",
                .symbol_name = "Z_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "Z L3 HIT L3BANK3",
                .symbol_name = "Z_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "Z L3 HIT L3BANK4",
                .symbol_name = "Z_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "Z L3 HIT L3BANK5",
                .symbol_name = "Z_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "Z L3 HIT L3BANK6",
                .symbol_name = "Z_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "Z L3 HIT L3BANK7",
                .symbol_name = "Z_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext11__z_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext11_Z_L3_HIT_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext12_L3_OUTPUT_READY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext12";
    metric_set->symbol_name = "Ext12";
    metric_set->hw_config_guid = "4678846c-99cd-4a3f-acb4-8f055f48da56";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext12__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK0",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK0",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK0_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK1",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK1",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK1_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK2",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK2",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK2_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK3",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK3",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK3_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK4",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK4",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK4_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK5",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK5",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK5_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK6",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK6",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK6_availability,
            },

            {
                .name = "L3 BANK INPUT AVAILABLE L3BANK7",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK7",
                .desc = "Percentage of time in which L3 bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_input_available_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_INPUT_AVAILABLE_L3BANK7_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK0",
                .symbol_name = "L3_OUTPUT_READY_L3BANK0",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK0_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK1",
                .symbol_name = "L3_OUTPUT_READY_L3BANK1",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK1_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK2",
                .symbol_name = "L3_OUTPUT_READY_L3BANK2",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK2_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK3",
                .symbol_name = "L3_OUTPUT_READY_L3BANK3",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK3_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK4",
                .symbol_name = "L3_OUTPUT_READY_L3BANK4",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK4_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK5",
                .symbol_name = "L3_OUTPUT_READY_L3BANK5",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK5_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK6",
                .symbol_name = "L3_OUTPUT_READY_L3BANK6",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK6_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK7",
                .symbol_name = "L3_OUTPUT_READY_L3BANK7",
                .desc = "Percentage of time in which L3 bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext12__l3_output_ready_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext12_L3_OUTPUT_READY_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext13_L3_SUPERQ_FULL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext13";
    metric_set->symbol_name = "Ext13";
    metric_set->hw_config_guid = "04d1f1c5-17e5-4104-b5a1-d62337b681b9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext13__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK0",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK0",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK0_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK1",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK1",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK1_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK2",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK2",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK2_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK3",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK3",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK3_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK4",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK4",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK4_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK5",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK5",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK5_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK6",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK6",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK6_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK7",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK7",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext13__l3_superq_full_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext13_L3_SUPERQ_FULL_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext14_L3_BUSY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext14_L3_BUSY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext14_L3_BUSY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext14_L3_BUSY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext14_L3_BUSY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext14_L3_BUSY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext14_L3_BUSY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext14_L3_BUSY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext14";
    metric_set->symbol_name = "Ext14";
    metric_set->hw_config_guid = "9312e21f-5d97-4058-a2fc-c7497c18f0a1";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext14__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK ACTIVE L3BANK0",
                .symbol_name = "L3_BUSY_L3BANK0",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK0_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK1",
                .symbol_name = "L3_BUSY_L3BANK1",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK1_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK2",
                .symbol_name = "L3_BUSY_L3BANK2",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK2_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK3",
                .symbol_name = "L3_BUSY_L3BANK3",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK3_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK4",
                .symbol_name = "L3_BUSY_L3BANK4",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK4_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK5",
                .symbol_name = "L3_BUSY_L3BANK5",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK5_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK6",
                .symbol_name = "L3_BUSY_L3BANK6",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK6_availability,
            },

            {
                .name = "L3 BANK ACTIVE L3BANK7",
                .symbol_name = "L3_BUSY_L3BANK7",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext14__l3_busy_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext14_L3_BUSY_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext15_L3_STALL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext15_L3_STALL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext15_L3_STALL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext15_L3_STALL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext15";
    metric_set->symbol_name = "Ext15";
    metric_set->hw_config_guid = "fd355e93-4edf-425c-99e6-8693a22ae3cd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext15__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK0",
                .symbol_name = "L3_STALL_L3BANK0",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext15__l3_stall_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext15_L3_STALL_L3BANK0_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK1",
                .symbol_name = "L3_STALL_L3BANK1",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext15__l3_stall_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext15_L3_STALL_L3BANK1_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK2",
                .symbol_name = "L3_STALL_L3BANK2",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext15__l3_stall_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext15_L3_STALL_L3BANK2_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK3",
                .symbol_name = "L3_STALL_L3BANK3",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext15__l3_stall_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext15_L3_STALL_L3BANK3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext16_L3_STALL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext16_L3_STALL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext16_L3_STALL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext16_L3_STALL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext16";
    metric_set->symbol_name = "Ext16";
    metric_set->hw_config_guid = "844efb3d-c453-4dd2-b556-7bac8e111b46";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext16__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BANK STALL L3BANK4",
                .symbol_name = "L3_STALL_L3BANK4",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext16__l3_stall_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext16_L3_STALL_L3BANK4_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK5",
                .symbol_name = "L3_STALL_L3BANK5",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext16__l3_stall_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext16_L3_STALL_L3BANK5_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK6",
                .symbol_name = "L3_STALL_L3BANK6",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext16__l3_stall_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext16_L3_STALL_L3BANK6_availability,
            },

            {
                .name = "L3 BANK STALL L3BANK7",
                .symbol_name = "L3_STALL_L3BANK7",
                .desc = "Percentage of time in which L3 bank stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext16__l3_stall_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "L3Cache",
                .availability = acmgt1_ext16_L3_STALL_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext17";
    metric_set->symbol_name = "Ext17";
    metric_set->hw_config_guid = "fadda67d-1b94-40d1-be89-759f78641ab2";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext17__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext17__load_store_cache_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext17__load_store_cache_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext17__load_store_cache_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext17__load_store_cache_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext18";
    metric_set->symbol_name = "Ext18";
    metric_set->hw_config_guid = "bdd021fa-a841-4f92-826f-c3ae681c68e6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext18__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext18__load_store_cache_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext18__load_store_cache_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext18__load_store_cache_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext18__load_store_cache_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext19_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext19";
    metric_set->symbol_name = "Ext19";
    metric_set->hw_config_guid = "1181d35b-bf9a-4640-82b8-e31e031ea8d3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext19_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext19__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext19__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext19__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext19__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext19__load_store_cache_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext19__load_store_cache_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext19__load_store_cache_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext19__load_store_cache_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext19_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext20_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext20";
    metric_set->symbol_name = "Ext20";
    metric_set->hw_config_guid = "aa39f75d-0a8a-43d1-9c51-bcd8c62cdfe6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext20_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext20__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext20__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext20__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext20__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext20__load_store_cache_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext20__load_store_cache_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext20__load_store_cache_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext20__load_store_cache_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "L1Cache",
                .availability = acmgt1_ext20_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext21";
    metric_set->symbol_name = "Ext21";
    metric_set->hw_config_guid = "ae58d1ad-8aed-4104-a8e2-443d7e800378";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext21__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext21__load_store_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext21__load_store_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext21__load_store_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext21__load_store_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext21_LOAD_STORE_CACHE_ACCESS_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext22";
    metric_set->symbol_name = "Ext22";
    metric_set->hw_config_guid = "c27ebd95-f242-4f4b-969a-9850f1081c30";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext22__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext22__load_store_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext22__load_store_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext22__load_store_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Load Store Cache accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext22__load_store_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext22_LOAD_STORE_CACHE_ACCESS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext23_LOAD_STORE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext23_LOAD_STORE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext23";
    metric_set->symbol_name = "Ext23";
    metric_set->hw_config_guid = "881a8616-b63f-4bb1-970a-73b40b762434";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext23__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE0",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext23__load_store_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext23_LOAD_STORE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE1",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext23__load_store_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext23_LOAD_STORE_CACHE_HIT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext24_LOAD_STORE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext24_LOAD_STORE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext24";
    metric_set->symbol_name = "Ext24";
    metric_set->hw_config_guid = "9fe09ad3-d296-4d41-ab19-270431f7ab29";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext24__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE2",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext24__load_store_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext24_LOAD_STORE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE3",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext24__load_store_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext24_LOAD_STORE_CACHE_HIT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext25_LOAD_STORE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext25_LOAD_STORE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext25_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext25";
    metric_set->symbol_name = "Ext25";
    metric_set->hw_config_guid = "e2016425-8755-4ca0-bc93-354ba7a6ca7a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext25_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext25__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext25__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext25__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext25__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE4",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext25__load_store_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext25_LOAD_STORE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE5",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext25__load_store_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext25_LOAD_STORE_CACHE_HIT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext26_LOAD_STORE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext26_LOAD_STORE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext26_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext26";
    metric_set->symbol_name = "Ext26";
    metric_set->hw_config_guid = "9fc2d1f6-7504-41f2-9f4b-96ff3307f6cb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext26_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext26__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext26__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext26__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext26__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE6",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext26__load_store_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext26_LOAD_STORE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE7",
                .desc = "Number of Load Store Cache hits.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext26__load_store_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext26_LOAD_STORE_CACHE_HIT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext27_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext27";
    metric_set->symbol_name = "Ext27";
    metric_set->hw_config_guid = "7bc1c162-2b4b-4cb8-b351-65be069d3f10";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext27_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext27__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext27__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext27__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext27__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE0",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE1",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE2",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE3",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE4",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE5",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE6",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE7",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext27__load_store_cache_l3_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext27_LOAD_STORE_CACHE_L3_READ_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext28";
    metric_set->symbol_name = "Ext28";
    metric_set->hw_config_guid = "afdf809e-962c-4af5-8e08-cd55b455dee9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext28__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE0",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE1",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE2",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE3",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE4",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE5",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE6",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE7",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext28__load_store_cache_l3_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext29";
    metric_set->symbol_name = "Ext29";
    metric_set->hw_config_guid = "4f22c4f0-68ce-46ad-91a7-272b517bfa2e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext29__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext29__load_store_cache_partial_write_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext29__load_store_cache_partial_write_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext29__load_store_cache_partial_write_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext29__load_store_cache_partial_write_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext30_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext30";
    metric_set->symbol_name = "Ext30";
    metric_set->hw_config_guid = "376f6937-f69d-41b0-a1ae-402dee9d42cb";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext30_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext30__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext30__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext30__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext30__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext30__load_store_cache_partial_write_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext30__load_store_cache_partial_write_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext30__load_store_cache_partial_write_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext30__load_store_cache_partial_write_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext30_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext31";
    metric_set->symbol_name = "Ext31";
    metric_set->hw_config_guid = "28e81769-8b4e-4a6f-a658-19901c71f724";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext31__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext31__xve_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext31__xve_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext32";
    metric_set->symbol_name = "Ext32";
    metric_set->hw_config_guid = "0efcc5a6-bbc5-4af3-bf07-db3597f314ab";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext32__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext32__xve_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext32__xve_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext33_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext33_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext33_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext33";
    metric_set->symbol_name = "Ext33";
    metric_set->hw_config_guid = "038bcd96-55da-41c0-b9ad-6d71e943f1b9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext33_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext33__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext33__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext33__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext33__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext33__xve_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext33_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext33__xve_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext33_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext34_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext34_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext34_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext34";
    metric_set->symbol_name = "Ext34";
    metric_set->hw_config_guid = "48d0ac9b-3e47-43c9-9779-3e2cdf315635";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext34_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext34__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext34__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext34__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext34__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext34__xve_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext34_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext34__xve_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext34_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext35";
    metric_set->symbol_name = "Ext35";
    metric_set->hw_config_guid = "ebe68cc1-ddda-412d-b9de-4616c4421712";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext35__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext35__xve_load_store_cache_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext35__xve_load_store_cache_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext36";
    metric_set->symbol_name = "Ext36";
    metric_set->hw_config_guid = "b305a4ce-2466-4172-97f1-a09a874f377c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext36__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext36__xve_load_store_cache_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext36__xve_load_store_cache_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext37_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext37_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext37_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext37";
    metric_set->symbol_name = "Ext37";
    metric_set->hw_config_guid = "8184361a-7e98-4f4d-b047-42c767d4c863";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext37_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext37__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext37__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext37__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext37__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext37__xve_load_store_cache_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext37_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext37__xve_load_store_cache_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext37_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext38_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext38_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext38_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext38";
    metric_set->symbol_name = "Ext38";
    metric_set->hw_config_guid = "0298d65d-a984-4f19-b968-1e65f072189d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext38_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext38__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext38__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext38__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext38__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext38__xve_load_store_cache_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext38_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext38__xve_load_store_cache_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext38_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext39";
    metric_set->symbol_name = "Ext39";
    metric_set->hw_config_guid = "602b3d8e-9299-4615-9739-fe44dd9b7102";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext39__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext39__xve_load_store_cache_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext39__xve_load_store_cache_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext40";
    metric_set->symbol_name = "Ext40";
    metric_set->hw_config_guid = "7595f984-7cd3-4b1c-8332-bacfd2b3a359";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext40__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext40__xve_load_store_cache_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext40__xve_load_store_cache_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext41_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext41_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext41_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext41";
    metric_set->symbol_name = "Ext41";
    metric_set->hw_config_guid = "61bf91ad-0dfa-421c-b503-0eed63b64ef5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext41_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext41__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext41__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext41__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext41__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext41__xve_load_store_cache_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext41_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext41__xve_load_store_cache_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext41_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext42_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext42_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext42_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext42";
    metric_set->symbol_name = "Ext42";
    metric_set->hw_config_guid = "a2f3417e-fbe1-4c26-a20c-509c7205445f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext42_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext42__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext42__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext42__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext42__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext42__xve_load_store_cache_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext42_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext42__xve_load_store_cache_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext42_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext43_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext43_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext43_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext43";
    metric_set->symbol_name = "Ext43";
    metric_set->hw_config_guid = "343460a0-c54f-4fe5-b7ac-6d9870a56aaf";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext43_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext43__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext43__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext43__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext43__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext43__xve_load_store_cache_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext43_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext43__xve_load_store_cache_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext43_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext44_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext44_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext44_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext44";
    metric_set->symbol_name = "Ext44";
    metric_set->hw_config_guid = "cfaeaf8e-4888-459f-8019-c3080595c528";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext44_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext44__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext44__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext44__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext44__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext44__xve_load_store_cache_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext44_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext44__xve_load_store_cache_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext44_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext45_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext45_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext45";
    metric_set->symbol_name = "Ext45";
    metric_set->hw_config_guid = "c50cb371-e940-4499-aa74-4e75bc131329";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext45__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext45__xve_load_store_cache_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext45_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext45__xve_load_store_cache_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext45_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext46_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext46_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext46_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext46";
    metric_set->symbol_name = "Ext46";
    metric_set->hw_config_guid = "b56a3837-111d-4ec1-8d3f-42e9e304d8f5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext46_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext46__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext46__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext46__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext46__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext46__xve_load_store_cache_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext46_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext46__xve_load_store_cache_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext46_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext47_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext47_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext47_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext47";
    metric_set->symbol_name = "Ext47";
    metric_set->hw_config_guid = "3725926f-9a84-4cc2-963c-2294f47c017c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext47_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext47__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext47__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext47__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext47__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext47__xve_load_store_cache_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext47_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext47__xve_load_store_cache_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext47_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext48_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext48_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext48_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext48";
    metric_set->symbol_name = "Ext48";
    metric_set->hw_config_guid = "357a3801-3f4e-4106-8f1e-c0bfe1c5f419";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext48_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext48__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext48__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext48__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext48__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext48__xve_load_store_cache_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext48_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext48__xve_load_store_cache_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext48_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext49_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext49_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext49_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext49";
    metric_set->symbol_name = "Ext49";
    metric_set->hw_config_guid = "8b324152-65d7-4b13-8fa9-cab57cd68471";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext49_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext49__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext49__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext49__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext49__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext49__xve_load_store_cache_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext49_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext49__xve_load_store_cache_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext49_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext50_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext50_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext50_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext50";
    metric_set->symbol_name = "Ext50";
    metric_set->hw_config_guid = "db09b08d-a300-4f2a-aeb0-b797e7073ef3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext50_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext50__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext50__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext50__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext50__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext50__xve_load_store_cache_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext50_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext50__xve_load_store_cache_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext50_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext51_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext51";
    metric_set->symbol_name = "Ext51";
    metric_set->hw_config_guid = "fc148084-3936-4dab-9b42-d7ba6ae1952d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext51_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext51__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext51__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext51__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext51__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext51__xve_load_store_cache_register_response_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext51__xve_load_store_cache_register_response_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext51__xve_load_store_cache_register_response_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext51__xve_load_store_cache_register_response_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext52_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext52";
    metric_set->symbol_name = "Ext52";
    metric_set->hw_config_guid = "f6a3c36f-9fd8-49c4-b25a-dbf26256bdc6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext52_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext52__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext52__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext52__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext52__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext52__xve_load_store_cache_register_response_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext52__xve_load_store_cache_register_response_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext52__xve_load_store_cache_register_response_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext52__xve_load_store_cache_register_response_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext52_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext53_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext53";
    metric_set->symbol_name = "Ext53";
    metric_set->hw_config_guid = "a9a91699-a2b3-4841-8641-4f09f04be7e1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext53_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext53__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext53__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext53__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext53__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext53__xve_slm_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext53__xve_slm_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext54_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext54";
    metric_set->symbol_name = "Ext54";
    metric_set->hw_config_guid = "c44659b1-937a-44bc-8819-9c1ae31d9bdd";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext54_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext54__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext54__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext54__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext54__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext54__xve_slm_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext54__xve_slm_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext55_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext55_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext55_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext55";
    metric_set->symbol_name = "Ext55";
    metric_set->hw_config_guid = "5bfd7ae1-27ea-4211-beb2-64565a49dfbe";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext55_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext55__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext55__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext55__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext55__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext55__xve_slm_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext55_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext55__xve_slm_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext55_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext56_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext56_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext56_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext56";
    metric_set->symbol_name = "Ext56";
    metric_set->hw_config_guid = "7aefc824-149a-4f75-abed-f6430f8d4eee";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext56_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext56__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext56__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext56__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext56__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext56__xve_slm_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext56_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext56__xve_slm_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext56_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext57_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext57";
    metric_set->symbol_name = "Ext57";
    metric_set->hw_config_guid = "0ccb67b5-7f31-4885-9973-d97e318a6f90";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext57_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext57__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext57__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext57__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext57__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext57__xve_slm_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext57__xve_slm_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext58_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext58";
    metric_set->symbol_name = "Ext58";
    metric_set->hw_config_guid = "af47d7b7-691b-4ec5-abfd-67ce50938fe4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext58_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext58__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext58__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext58__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext58__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext58__xve_slm_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext58__xve_slm_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext59_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext59";
    metric_set->symbol_name = "Ext59";
    metric_set->hw_config_guid = "0df81caa-d128-4f0e-9eff-69e0359fedf1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext59_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext59__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext59__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext59__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext59__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext59__xve_slm_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext59__xve_slm_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext59_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext60_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext60";
    metric_set->symbol_name = "Ext60";
    metric_set->hw_config_guid = "09e71710-e49d-4d9e-b7f8-0e597aabf25b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext60_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext60__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext60__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext60__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext60__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext60__xve_slm_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext60__xve_slm_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext60_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext61_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext61";
    metric_set->symbol_name = "Ext61";
    metric_set->hw_config_guid = "374c4608-89a8-46d3-92fa-d4848e4a7a95";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext61_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext61__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext61__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext61__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext61__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext61__xve_slm_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext61__xve_slm_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext62_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext62";
    metric_set->symbol_name = "Ext62";
    metric_set->hw_config_guid = "1013ed95-4958-4cfe-8fbc-1482c07046cb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext62_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext62__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext62__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext62__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext62__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext62__xve_slm_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext62__xve_slm_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext63_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext63_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext63_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext63";
    metric_set->symbol_name = "Ext63";
    metric_set->hw_config_guid = "7a3c4561-56d3-4b61-a619-ed8c1887e034";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext63_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext63__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext63__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext63__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext63__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext63__xve_slm_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext63_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext63__xve_slm_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext63_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext64_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext64_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext64_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext64";
    metric_set->symbol_name = "Ext64";
    metric_set->hw_config_guid = "7d50a975-2d8d-48c2-ae61-86decd3aba1d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext64_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext64__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext64__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext64__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext64__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext64__xve_slm_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext64_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext64__xve_slm_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext64_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext65_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext65";
    metric_set->symbol_name = "Ext65";
    metric_set->hw_config_guid = "c036e0c0-c23a-45ec-8b24-7ab7577b18d1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext65_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext65__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext65__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext65__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext65__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext65__xve_slm_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext66_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext66";
    metric_set->symbol_name = "Ext66";
    metric_set->hw_config_guid = "df8127a7-0efc-487e-a819-a20c2471e30b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext66_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext66__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext66__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext66__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext66__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext66__xve_slm_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext67";
    metric_set->symbol_name = "Ext67";
    metric_set->hw_config_guid = "f9d2c7da-14c9-45a4-97f5-a0d58dd3a1aa";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext67__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext67__xve_slm_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext68_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext68";
    metric_set->symbol_name = "Ext68";
    metric_set->hw_config_guid = "210f665b-abaa-4389-95e3-7cad6f71db8b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext68_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext68__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext68__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext68__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext68__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext68__xve_slm_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext69_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext69_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext69";
    metric_set->symbol_name = "Ext69";
    metric_set->hw_config_guid = "26eeaeca-61f0-46ba-b6ad-effb4ea076ae";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext69_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext69__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext69__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext69__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext69__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext69__xve_slm_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext69_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext70_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext70_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext70";
    metric_set->symbol_name = "Ext70";
    metric_set->hw_config_guid = "18a0a208-526a-4705-9b06-9145f03433ea";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext70_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext70__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext70__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext70__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext70__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext70__xve_slm_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext70_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext71_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext71_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext71";
    metric_set->symbol_name = "Ext71";
    metric_set->hw_config_guid = "0677d73a-a563-47ac-8b11-9c7c3371fc04";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext71_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext71__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext71__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext71__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext71__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext71__xve_slm_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext71_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext72_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext72_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext72";
    metric_set->symbol_name = "Ext72";
    metric_set->hw_config_guid = "0a10b421-f9ee-4147-81e2-b2ceeb74697f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext72_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext72__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext72__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext72__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext72__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext72__xve_slm_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext72_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext73_DATAPORT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext73_DATAPORT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext73_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext73";
    metric_set->symbol_name = "Ext73";
    metric_set->hw_config_guid = "4051668d-2020-4f10-a9e7-e840455b125b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext73_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext73__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext73__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE0",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext73__dataport_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext73_DATAPORT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE1",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext73__dataport_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext73_DATAPORT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext73__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext73__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext74_DATAPORT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext74_DATAPORT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext74_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext74";
    metric_set->symbol_name = "Ext74";
    metric_set->hw_config_guid = "0548ee0d-a4b2-42a7-86c6-4171ed191bec";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext74_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext74__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext74__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE2",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext74__dataport_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext74_DATAPORT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE3",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext74__dataport_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext74_DATAPORT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext74__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext74__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext75_DATAPORT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext75_DATAPORT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext75_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext75";
    metric_set->symbol_name = "Ext75";
    metric_set->hw_config_guid = "4604dea5-4e86-4713-b82d-fce110cb82f8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext75_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext75__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext75__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE4",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext75__dataport_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext75_DATAPORT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE5",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext75__dataport_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext75_DATAPORT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext75__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext75__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext76_DATAPORT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext76_DATAPORT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext76_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext76";
    metric_set->symbol_name = "Ext76";
    metric_set->hw_config_guid = "d4171f1f-6e14-41e1-8b9d-0e28077aca25";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext76_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext76__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext76__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE6",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext76__dataport_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext76_DATAPORT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE7",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext76__dataport_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext76_DATAPORT_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext76__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext76__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext77_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext77";
    metric_set->symbol_name = "Ext77";
    metric_set->hw_config_guid = "8e91f318-149b-4ffe-9b51-42dd9b2c80a5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext77_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext77__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext77__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE0",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext77__dataport_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE1",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext77__dataport_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE2",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext77__dataport_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE3",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext77__dataport_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext77_DATAPORT_OUTPUT_READY_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext77__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext77__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext78_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext78";
    metric_set->symbol_name = "Ext78";
    metric_set->hw_config_guid = "bf68f6bc-fdcb-4dbe-a923-abaeb72e8af6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext78_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext78__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext78__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE4",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext78__dataport_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE5",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext78__dataport_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE6",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext78__dataport_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE7",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext78__dataport_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Dataport",
                .availability = acmgt1_ext78_DATAPORT_OUTPUT_READY_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext78__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext78__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext79_DATAPORT_BYTE_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext79_DATAPORT_BYTE_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext79_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext79";
    metric_set->symbol_name = "Ext79";
    metric_set->hw_config_guid = "76b52ef9-7a1b-4475-b3bc-3a035acd32e7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext79_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext79__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext79__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE0",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE0",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext79__dataport_byte_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext79_DATAPORT_BYTE_READ_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE1",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE1",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext79__dataport_byte_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext79_DATAPORT_BYTE_READ_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext79__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext79__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext80_DATAPORT_BYTE_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext80_DATAPORT_BYTE_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext80_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext80";
    metric_set->symbol_name = "Ext80";
    metric_set->hw_config_guid = "171d99e0-0ace-4af7-8702-19e9fbb04a46";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext80_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext80__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext80__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE2",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE2",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext80__dataport_byte_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext80_DATAPORT_BYTE_READ_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE3",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE3",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext80__dataport_byte_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext80_DATAPORT_BYTE_READ_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext80__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext80__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext81_DATAPORT_BYTE_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext81_DATAPORT_BYTE_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext81_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext81";
    metric_set->symbol_name = "Ext81";
    metric_set->hw_config_guid = "f399ee12-9656-47fe-8566-416a8e4e4c07";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext81_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext81__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext81__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE4",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE4",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext81__dataport_byte_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext81_DATAPORT_BYTE_READ_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE5",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE5",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext81__dataport_byte_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext81_DATAPORT_BYTE_READ_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext81__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext81__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext82_DATAPORT_BYTE_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext82_DATAPORT_BYTE_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext82_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext82";
    metric_set->symbol_name = "Ext82";
    metric_set->hw_config_guid = "766bbe37-ffda-41f0-92da-e31184140e43";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext82_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext82__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext82__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE6",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE6",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext82__dataport_byte_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext82_DATAPORT_BYTE_READ_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE7",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE7",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext82__dataport_byte_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext82_DATAPORT_BYTE_READ_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext82__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext82__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext83_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext83";
    metric_set->symbol_name = "Ext83";
    metric_set->hw_config_guid = "4d5d9009-c75e-4655-8374-503fd68ac0c7";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext83_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext83__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext83__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE0",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE0",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE1",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE1",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE1_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE2",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE2",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE3",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE3",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE3_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE4",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE4",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE5",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE5",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE5_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE6",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE6",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE7",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE7",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext83__dataport_byte_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_BYTE_WRITE_XECORE7_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of cacheline requests from the Dataport to the texture cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext83__dataport_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext83__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext83__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext84_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext84";
    metric_set->symbol_name = "Ext84";
    metric_set->hw_config_guid = "fd091d19-b48d-49d2-b99e-c5505624daa3";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext84_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext84__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext84__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE0",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE1",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE2",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE3",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE4",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE5",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE6",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE7",
                .desc = "Number of cache requests from the Dataport to the texture cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext84__dataport_texture_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext84_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext84__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext84__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext85_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext85";
    metric_set->symbol_name = "Ext85";
    metric_set->hw_config_guid = "d45a3f38-372d-4757-88cf-5589035652d5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext85_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext85__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext85__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext85__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext85__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext85__xve_dataport_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext85__xve_dataport_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext85__xve_dataport_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext85__xve_dataport_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext86_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext86";
    metric_set->symbol_name = "Ext86";
    metric_set->hw_config_guid = "46f2e8eb-1a50-499e-9096-66f79932703e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext86_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext86__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext86__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext86__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext86__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext86__xve_dataport_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext86__xve_dataport_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext86__xve_dataport_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext86__xve_dataport_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext87_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext87";
    metric_set->symbol_name = "Ext87";
    metric_set->hw_config_guid = "35a680fa-e0c7-4e60-9a42-4e5c67d90b4d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext87_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext87__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext87__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext87__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext87__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext87__xve_dataport_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext87__xve_dataport_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext87__xve_dataport_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext87__xve_dataport_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext88_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext88";
    metric_set->symbol_name = "Ext88";
    metric_set->hw_config_guid = "e1d0a1c4-41c7-4d82-a6f0-42ea537e5664";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext88_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext88__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext88__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext88__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext88__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext88__xve_dataport_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext88__xve_dataport_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext88__xve_dataport_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext88__xve_dataport_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext91_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext91";
    metric_set->symbol_name = "Ext91";
    metric_set->hw_config_guid = "c26ba023-58d3-4ec7-9282-f2638a292912";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext91_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext91__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext91__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext91__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext91__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext91__xve_dataport_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext91__xve_dataport_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext91__xve_dataport_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext91__xve_dataport_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext92_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext92";
    metric_set->symbol_name = "Ext92";
    metric_set->hw_config_guid = "7e5a8ef5-b434-4bf1-81f0-eeddaa072d37";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext92_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext92__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext92__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext92__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext92__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext92__xve_dataport_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext92__xve_dataport_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext92__xve_dataport_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext92__xve_dataport_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext93_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext93";
    metric_set->symbol_name = "Ext93";
    metric_set->hw_config_guid = "917a8688-0aa2-4b9a-a1a1-60dc016b17e6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext93_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext93__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext93__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext93__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext93__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext93__xve_dataport_register_response_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt1__ext93__xve_dataport_register_response_count_xecore1__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext94_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext94";
    metric_set->symbol_name = "Ext94";
    metric_set->hw_config_guid = "dad96cfd-65c0-470c-a9d2-33d7881234c0";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext94_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext94__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext94__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext94__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext94__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt1__ext94__xve_dataport_register_response_count_xecore2__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt1__ext94__xve_dataport_register_response_count_xecore3__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext95_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext95";
    metric_set->symbol_name = "Ext95";
    metric_set->hw_config_guid = "811672a2-3bd6-473e-bd4b-dae0a5786a00";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext95_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext95__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext95__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext95__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext95__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt1__ext95__xve_dataport_register_response_count_xecore4__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt1__ext95__xve_dataport_register_response_count_xecore5__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext96_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext96";
    metric_set->symbol_name = "Ext96";
    metric_set->hw_config_guid = "91ebb988-2cc5-4cb9-b071-3a9d76f42b55";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext96_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext96__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext96__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext96__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext96__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt1__ext96__xve_dataport_register_response_count_xecore6__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = acmgt1__ext96__xve_dataport_register_response_count_xecore7__read,
                .max_float = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext97_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext97";
    metric_set->symbol_name = "Ext97";
    metric_set->hw_config_guid = "3e446a1f-d62b-4ea4-bbf3-845dc7f437e4";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext97_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext97__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext97__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext97__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext97__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext97__xve_dataport_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext98_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext98";
    metric_set->symbol_name = "Ext98";
    metric_set->hw_config_guid = "5ff858aa-50d0-44b9-bbf7-d07881ecdd9c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext98_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext98__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext98__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext98__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext98__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE0",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext98__sampler_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE1",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext98__sampler_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE2",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext98__sampler_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE3",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext98__sampler_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext98_SAMPLER_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext99_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext99";
    metric_set->symbol_name = "Ext99";
    metric_set->hw_config_guid = "ba34845b-431b-41c8-9d51-5c8be2f0ac4c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext99_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext99__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext99__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext99__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext99__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE4",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext99__sampler_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE5",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext99__sampler_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE6",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext99__sampler_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE7",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext99__sampler_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext99_SAMPLER_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext100_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext100";
    metric_set->symbol_name = "Ext100";
    metric_set->hw_config_guid = "978e5720-eb5a-46fc-aa24-7a34a853130b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext100_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext100__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext100__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext100__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext100__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE0",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE0",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE1",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE1",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE2",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE2",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE3",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE3",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE4",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE4",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE5",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE5",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE6",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE6",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE7",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE7",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext100__sampler_memory_latency_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext101_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext101";
    metric_set->symbol_name = "Ext101";
    metric_set->hw_config_guid = "9320b9d5-43c9-435d-b0ed-ec8a565d742d";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext101_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext101__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext101__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext101__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext101__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE0",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE1",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE2",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE3",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE4",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE5",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE6",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE7",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE0",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE1",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE2",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE3",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE4",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE5",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE6",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE7",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext101__thread_dispatch_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext101_THREAD_DISPATCH_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext102_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext102";
    metric_set->symbol_name = "Ext102";
    metric_set->hw_config_guid = "ff32c8bc-39ed-4dbe-9d88-2d2cdb973872";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext102_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext102__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext102__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext102__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext102__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE0",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE1",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE2",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE3",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE4",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE5",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE6",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE7",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext102__sampler_texture_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
                .availability = acmgt1_ext102_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext103_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext103";
    metric_set->symbol_name = "Ext103";
    metric_set->hw_config_guid = "73a834ac-afbe-4ca1-af18-af9aabc0280a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext103_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext103__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext103__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext103__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext103__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE0",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE1",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE2",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE3",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE4",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE5",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE6",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE7",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext103__sampler_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = acmgt1_ext103_SAMPLER_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext104_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext104_GPGPU_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext104_GPGPU_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext104_TASK_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext104_TASK_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext104_TASK_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext104_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext104";
    metric_set->symbol_name = "Ext104";
    metric_set->hw_config_guid = "eb13a257-4c07-469e-8bef-55da7dff1b41";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext104_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE0",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext104__async_gpgpu_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext104_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext104__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext104__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE2",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext104__gpgpu_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext104_GPGPU_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE3",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext104__gpgpu_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext104_GPGPU_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext104__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext104__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE2",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext104__task_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext104_TASK_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE3",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext104__task_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext104_TASK_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE0",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext104__task_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext104_TASK_THREAD_EXIT_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt1_ext105_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext105_GPGPU_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext105_GPGPU_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext105_TASK_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext105_TASK_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext105_TASK_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext105_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext105";
    metric_set->symbol_name = "Ext105";
    metric_set->hw_config_guid = "0343e7a1-8f7d-44b8-a75c-73baef6cc22b";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext105_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE1",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext105__async_gpgpu_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext105_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext105__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext105__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE4",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext105__gpgpu_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext105_GPGPU_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE5",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext105__gpgpu_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext105_GPGPU_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext105__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext105__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE4",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext105__task_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext105_TASK_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE5",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext105__task_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext105_TASK_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE1",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext105__task_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext105_TASK_THREAD_EXIT_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt1_ext106_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext106_GPGPU_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext106_GPGPU_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext106_TASK_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext106_TASK_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext106_TASK_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext106_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext106";
    metric_set->symbol_name = "Ext106";
    metric_set->hw_config_guid = "048a2bcb-b786-4b51-b350-8908f50e69d7";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext106_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE2",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext106__async_gpgpu_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext106_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext106__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext106__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE6",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext106__gpgpu_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext106_GPGPU_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE7",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext106__gpgpu_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext106_GPGPU_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext106__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext106__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE6",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext106__task_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext106_TASK_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE7",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext106__task_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext106_TASK_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE2",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext106__task_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext106_TASK_THREAD_EXIT_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt1_ext107_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext107_GPGPU_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext107_GPGPU_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext107_TASK_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext107_TASK_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext107_TASK_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext107_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext107";
    metric_set->symbol_name = "Ext107";
    metric_set->hw_config_guid = "e393956e-78b0-4f7e-8482-cb13c1706ecd";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext107_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE3",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext107__async_gpgpu_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext107_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext107__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext107__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE0",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext107__gpgpu_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext107_GPGPU_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE1",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext107__gpgpu_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext107_GPGPU_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext107__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext107__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE0",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext107__task_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext107_TASK_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE1",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext107__task_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext107_TASK_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE3",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext107__task_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext107_TASK_THREAD_EXIT_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt1_ext108_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext108_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext108_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext108_TASK_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext108_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext108";
    metric_set->symbol_name = "Ext108";
    metric_set->hw_config_guid = "2ea41c1b-4751-446f-b178-9aa17cf85d72";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext108_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE6",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext108__async_gpgpu_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext108_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE7",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext108__async_gpgpu_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext108_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE4",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext108__async_gpgpu_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext108_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext108__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext108__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext108__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext108__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE4",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext108__task_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext108_TASK_THREAD_EXIT_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext109_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext109_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext109_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext109_TASK_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext109_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext109";
    metric_set->symbol_name = "Ext109";
    metric_set->hw_config_guid = "32b61c78-b7d2-4162-8964-dbf47f187290";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext109_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE1",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext109__async_gpgpu_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext109_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE2",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext109__async_gpgpu_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext109_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE5",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext109__async_gpgpu_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext109_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext109__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext109__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext109__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext109__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE5",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext109__task_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext109_TASK_THREAD_EXIT_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext110_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext110_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext110_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext110_TASK_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext110_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext110";
    metric_set->symbol_name = "Ext110";
    metric_set->hw_config_guid = "536ed3af-e1e6-4f5a-be8b-3eabfa9487fa";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext110_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE3",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext110__async_gpgpu_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext110_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE4",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext110__async_gpgpu_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext110_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE6",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext110__async_gpgpu_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext110_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext110__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext110__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext110__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext110__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE6",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext110__task_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext110_TASK_THREAD_EXIT_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext111_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext111_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext111_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext111_TASK_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext111_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext111";
    metric_set->symbol_name = "Ext111";
    metric_set->hw_config_guid = "11eedd05-3490-4a57-8ea7-56e1d2dd066a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext111_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE0",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext111__async_gpgpu_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext111_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "ASYNC GPGPU THREADGROUP COUNT XECORE5",
                .symbol_name = "ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of Async GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext111__async_gpgpu_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext111_ASYNC_GPGPU_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE7",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext111__async_gpgpu_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext111_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext111__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext111__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext111__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext111__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE7",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext111__task_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext111_TASK_THREAD_EXIT_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext112_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext112";
    metric_set->symbol_name = "Ext112";
    metric_set->hw_config_guid = "2324dd37-ac7e-4a5e-8d0c-f7b94fd36961";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext112_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext112__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext112__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext112__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext112__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 INPUT AVAILABLE XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue0_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE0_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 INPUT AVAILABLE XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Spawner has input available on queue 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext112__threadgroup_dispatch_queue1_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext112_THREADGROUP_DISPATCH_QUEUE1_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext113_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext113";
    metric_set->symbol_name = "Ext113";
    metric_set->hw_config_guid = "03551880-b834-45f0-8b71-e61f548e5d83";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext113_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext113__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext113__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext113__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext113__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE0",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE1",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE2",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE3",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE4",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE5",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE6",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_XECORE7",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext113__thread_dispatch_ps_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext113_THREAD_DISPATCH_PS_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext114_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext114";
    metric_set->symbol_name = "Ext114";
    metric_set->hw_config_guid = "8d368e2f-7c30-4a9e-a20f-b098105300b7";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext114_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext114__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext114__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext114__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext114__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext114__thread_dispatch_queue0_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext115_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext115";
    metric_set->symbol_name = "Ext115";
    metric_set->hw_config_guid = "cb96d66c-bfc4-4de8-a3dc-5d67c5acda38";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext115_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext115__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext115__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext115__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext115__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext115__thread_dispatch_queue1_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext115_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext116_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext116";
    metric_set->symbol_name = "Ext116";
    metric_set->hw_config_guid = "2355cc8b-c596-479d-ab76-16c2d3644b5b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext116_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext116__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext116__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext116__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext116__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext116__threadgroup_dispatch_resource_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext117_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext117";
    metric_set->symbol_name = "Ext117";
    metric_set->hw_config_guid = "006584d5-ebb1-4d21-a8ab-cfa66e75dae4";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext117_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext117__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext117__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext117__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext117__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext117__threadgroup_dispatch_resource_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext118_AMFS_CACHE_HIT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_AMFS_CACHE_MISS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_AMFS_STALL_ALL_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_AMFS_STALL_ANY_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_RENDER_CACHE_HIT_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_RENDER_CACHE_READ_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext118_RENDER_CACHE_WRITE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext118_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext118";
    metric_set->symbol_name = "Ext118";
    metric_set->hw_config_guid = "9ae38060-8785-44ec-a758-4082b94af42d";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext118_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE0",
                .symbol_name = "AMFS_CACHE_HIT_SLICE0",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext118__amfs_cache_hit_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext118_AMFS_CACHE_HIT_SLICE0_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE0",
                .symbol_name = "AMFS_CACHE_MISS_SLICE0",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext118__amfs_cache_miss_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext118_AMFS_CACHE_MISS_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext118__amfs_stall_all_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt1_ext118_AMFS_STALL_ALL_INPUT_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext118__amfs_stall_any_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt1_ext118_AMFS_STALL_ANY_INPUT_SLICE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext118__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext118__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext118__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext118__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE0",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE0",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext118__render_cache_hit_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext118_RENDER_CACHE_HIT_L3NODE0_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE0",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE0",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext118__render_cache_input_available_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext118_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE0",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE0",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext118__render_cache_output_ready_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext118_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE0",
                .symbol_name = "RENDER_CACHE_READ_L3NODE0",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext118__render_cache_read_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext118_RENDER_CACHE_READ_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE0",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE0",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext118__render_cache_write_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext118_RENDER_CACHE_WRITE_L3NODE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt1_ext119_AMFS_CACHE_HIT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_AMFS_CACHE_MISS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_AMFS_STALL_ALL_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_AMFS_STALL_ANY_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_RENDER_CACHE_HIT_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_RENDER_CACHE_READ_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext119_RENDER_CACHE_WRITE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext119_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext119";
    metric_set->symbol_name = "Ext119";
    metric_set->hw_config_guid = "8ef448b2-776c-4d73-8a44-eabfb2fcc888";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext119_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE1",
                .symbol_name = "AMFS_CACHE_HIT_SLICE1",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext119__amfs_cache_hit_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext119_AMFS_CACHE_HIT_SLICE1_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE1",
                .symbol_name = "AMFS_CACHE_MISS_SLICE1",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext119__amfs_cache_miss_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext119_AMFS_CACHE_MISS_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext119__amfs_stall_all_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt1_ext119_AMFS_STALL_ALL_INPUT_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext119__amfs_stall_any_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "AMFS",
                .availability = acmgt1_ext119_AMFS_STALL_ANY_INPUT_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext119__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext119__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext119__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext119__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE1",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE1",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext119__render_cache_hit_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext119_RENDER_CACHE_HIT_L3NODE1_availability,
            },

            {
                .name = "RENDER_CACHE_INPUT_AVAILABLE _L3NODE1",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE1",
                .desc = "Percentage of time when render cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext119__render_cache_input_available_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext119_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability,
            },

            {
                .name = "RENDER_CACHE_OUTPUT_READY _L3NODE1",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE1",
                .desc = "Percentage of time when render cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext119__render_cache_output_ready_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext119_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE1",
                .symbol_name = "RENDER_CACHE_READ_L3NODE1",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext119__render_cache_read_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext119_RENDER_CACHE_READ_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE1",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE1",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext119__render_cache_write_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext119_RENDER_CACHE_WRITE_L3NODE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext120_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext120";
    metric_set->symbol_name = "Ext120";
    metric_set->hw_config_guid = "3b5b473c-259e-4eb7-8643-a88b53aa2e1c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext120_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext120__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext120__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext120__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext120__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE0",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext120__pixel_post_process_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE1",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext120__pixel_post_process_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE2",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext120__pixel_post_process_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE3",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext120__pixel_post_process_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext121_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext121";
    metric_set->symbol_name = "Ext121";
    metric_set->hw_config_guid = "f2045966-fcf0-479b-aef4-0358574f67ee";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext121_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext121__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext121__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext121__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext121__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE4",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext121__pixel_post_process_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE5",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext121__pixel_post_process_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE6",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext121__pixel_post_process_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE7",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext121__pixel_post_process_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext122_AMFS_4X4_SHADING_REQUEST_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_AMFS_4X4_SHADING_REQUEST_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext122_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext122";
    metric_set->symbol_name = "Ext122";
    metric_set->hw_config_guid = "e175d8c3-7672-4e57-83a0-87caf56a5440";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext122_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE0",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE0",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext122__amfs_4_x4_shading_request_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext122_AMFS_4X4_SHADING_REQUEST_SLICE0_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE1",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE1",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext122__amfs_4_x4_shading_request_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext122_AMFS_4X4_SHADING_REQUEST_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext122__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext122__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE2",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE3",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__color_pipe_cache_latency1_stall_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext122__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext122__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__pixel_post_process_output_ready_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__pixel_post_process_output_ready_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__pixel_post_process_output_ready_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext122__pixel_post_process_output_ready_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt1_ext123_AMFS_L3_ACCESS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext123_AMFS_L3_ACCESS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext123_AMFS_L3_ATOMIC_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext123_AMFS_L3_ATOMIC_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext123_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext123";
    metric_set->symbol_name = "Ext123";
    metric_set->hw_config_guid = "7f7218b1-462c-4f08-8032-86e426dbc83d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext123_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 ACCESS SLICE0",
                .symbol_name = "AMFS_L3_ACCESS_SLICE0",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext123__amfs_l3_access_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext123_AMFS_L3_ACCESS_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE1",
                .symbol_name = "AMFS_L3_ACCESS_SLICE1",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext123__amfs_l3_access_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext123_AMFS_L3_ACCESS_SLICE1_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE0",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE0",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext123__amfs_l3_atomic_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext123_AMFS_L3_ATOMIC_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE1",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE1",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext123__amfs_l3_atomic_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext123_AMFS_L3_ATOMIC_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext123__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext123__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext123__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext123__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE0",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext123__ps_output_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE1",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext123__ps_output_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE1_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE2",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext123__ps_output_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE3",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext123__ps_output_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext123_PS_OUTPUT_AVAILABLE_CPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext124_CLIPPER_INPUT_VERTEX_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_CLIPPER_INPUT_VERTEX_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_VS_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext124_VS_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext124_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext124";
    metric_set->symbol_name = "Ext124";
    metric_set->hw_config_guid = "bd7a8af3-2d23-4c95-9cb1-429840dfc38f";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext124_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext124__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext124__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE0",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE0",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext124__clipper_input_vertex_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext124_CLIPPER_INPUT_VERTEX_SLICE0_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE1",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE1",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext124__clipper_input_vertex_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext124_CLIPPER_INPUT_VERTEX_SLICE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext124__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext124__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE0",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext124__streamout_output_vertex_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext124_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE1",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext124__streamout_output_vertex_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext124_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE0",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext124__vertex_fetch_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext124_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE1",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext124__vertex_fetch_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext124_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE0",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext124__vertex_fetch_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext124_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE1",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext124__vertex_fetch_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext124_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE0",
                .symbol_name = "VS_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext124__vs_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext124_VS_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE1",
                .symbol_name = "VS_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext124__vs_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext124_VS_OUTPUT_READY_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt1_ext125_CLIPPER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext125_CLIPPER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext125_CLIPPER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext125_CLIPPER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext125_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext125_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext125_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext125";
    metric_set->symbol_name = "Ext125";
    metric_set->hw_config_guid = "2e16a8a7-613a-4df1-91bf-eec73d281822";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext125_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext125__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext125__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE0",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext125__clipper_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext125_CLIPPER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE1",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext125__clipper_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext125_CLIPPER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE0",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext125__clipper_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext125_CLIPPER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE1",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext125__clipper_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext125_CLIPPER_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE0",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext125__clipper_primitive_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext125_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE1",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext125__clipper_primitive_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext125_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext125__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext125__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool acmgt1_ext126_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_STRIPSFAN_OBJECTS_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_STRIPSFAN_OBJECTS_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_STRIPSFAN_OBJECT_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_STRIPSFAN_OBJECT_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_STRIPSFAN_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext126_STRIPSFAN_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext126_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext126";
    metric_set->symbol_name = "Ext126";
    metric_set->hw_config_guid = "7cddf3f3-4ed8-484d-b8c7-82a4857ad030";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext126_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext126__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext126__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__clipper_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext126_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__clipper_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext126_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext126__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext126__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__rasterizer_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt1_ext126_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__rasterizer_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
                .availability = acmgt1_ext126_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE0",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE0",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__stripsfan_objects_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext126_STRIPSFAN_OBJECTS_CULL_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE1",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE1",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__stripsfan_objects_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext126_STRIPSFAN_OBJECTS_CULL_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE0",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE0",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__stripsfan_object_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext126_STRIPSFAN_OBJECT_COUNT_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE1",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE1",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext126__stripsfan_object_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext126_STRIPSFAN_OBJECT_COUNT_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE0",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext126__stripsfan_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext126_STRIPSFAN_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE1",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext126__stripsfan_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Geometry",
                .availability = acmgt1_ext126_STRIPSFAN_OUTPUT_READY_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool acmgt1_ext127_CLIPPER_PRIMITIVE_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext127_CLIPPER_PRIMITIVE_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext127_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext127_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext127_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext127_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext127_RASTERIZER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext127_RASTERIZER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext127_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext127";
    metric_set->symbol_name = "Ext127";
    metric_set->hw_config_guid = "cc78dbe3-bf19-4e4f-8957-c75488d8a47b";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext127_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext127__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext127__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE0",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext127__clipper_primitive_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext127_CLIPPER_PRIMITIVE_CULL_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE1",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext127__clipper_primitive_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext127_CLIPPER_PRIMITIVE_CULL_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext127__clipper_primitive_far_near_clip_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext127_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext127__clipper_primitive_far_near_clip_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Geometry",
                .availability = acmgt1_ext127_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext127__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext127__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE0",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext127__rasterizer_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_ext127_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE1",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext127__rasterizer_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_ext127_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE0",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext127__rasterizer_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_ext127_RASTERIZER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE1",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext127__rasterizer_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "Rasterizer",
                .availability = acmgt1_ext127_RASTERIZER_OUTPUT_READY_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext128_URB_CROSS_SLICE_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext128_URB_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext128_URB_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext128_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext128";
    metric_set->symbol_name = "Ext128";
    metric_set->hw_config_guid = "9722a829-b7e5-4716-b62e-ff6cb930232b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext128_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext128__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext128__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext128__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext128__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE0",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE0",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext128__urb_cross_slice_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt1_ext128_URB_CROSS_SLICE_READ_SLICE0_availability,
            },

            {
                .name = "URB READ SLICE0",
                .symbol_name = "URB_READ_SLICE0",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext128__urb_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt1_ext128_URB_READ_SLICE0_availability,
            },

            {
                .name = "URB WRITE SLICE0",
                .symbol_name = "URB_WRITE_SLICE0",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext128__urb_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt1_ext128_URB_WRITE_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext129_URB_CROSS_SLICE_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext129_URB_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext129_URB_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext129_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext129";
    metric_set->symbol_name = "Ext129";
    metric_set->hw_config_guid = "4d7bb9a8-4b02-435a-b2be-16a2314c421d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext129_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext129__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext129__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext129__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext129__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE1",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE1",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext129__urb_cross_slice_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt1_ext129_URB_CROSS_SLICE_READ_SLICE1_availability,
            },

            {
                .name = "URB READ SLICE1",
                .symbol_name = "URB_READ_SLICE1",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext129__urb_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt1_ext129_URB_READ_SLICE1_availability,
            },

            {
                .name = "URB WRITE SLICE1",
                .symbol_name = "URB_WRITE_SLICE1",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext129__urb_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "URB",
                .availability = acmgt1_ext129_URB_WRITE_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext130_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext130";
    metric_set->symbol_name = "Ext130";
    metric_set->hw_config_guid = "307951f8-0159-4d0c-bc8f-04fee7247e0a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext130_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext130__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext130__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext130__early_depth_stencil_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext130__early_depth_stencil_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext130__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext130__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext131_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext131";
    metric_set->symbol_name = "Ext131";
    metric_set->hw_config_guid = "aa04f1fa-826e-4b25-a7a6-4fbb4a7d0dd2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext131_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext131__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext131__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext131__early_depth_stencil_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext131__early_depth_stencil_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext131__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext131__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext132_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext132";
    metric_set->symbol_name = "Ext132";
    metric_set->hw_config_guid = "9121bb2c-a28d-4796-a60b-52905e317576";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext132_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext132__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext132__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext132__early_depth_stencil_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext132__early_depth_stencil_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext132__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext132__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext133_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext133";
    metric_set->symbol_name = "Ext133";
    metric_set->hw_config_guid = "14a8d00b-a361-4bc5-94fe-4664b837cc56";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext133_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext133__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext133__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext133__early_depth_stencil_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext133__early_depth_stencil_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext133__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext133__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext134_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext134_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext134";
    metric_set->symbol_name = "Ext134";
    metric_set->hw_config_guid = "74fda750-6436-4a97-897b-8eff0a63de70";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext134_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext134__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext134__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext134__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext134__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext134__hiz_depth_test_ambig_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext134_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext135_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext135_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext135";
    metric_set->symbol_name = "Ext135";
    metric_set->hw_config_guid = "1712c473-6635-49af-a6da-43c724c96dcd";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext135_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext135__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext135__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext135__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext135__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext135__hiz_depth_test_ambig_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext135_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext136_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext136_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext136";
    metric_set->symbol_name = "Ext136";
    metric_set->hw_config_guid = "5c1a57d6-2dff-48ca-98bf-02c71a22057a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext136_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext136__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext136__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext136__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext136__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext136__hiz_depth_test_ambig_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext136_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext137_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext137_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext137";
    metric_set->symbol_name = "Ext137";
    metric_set->hw_config_guid = "6ede1a62-069a-4b3d-8b17-000005541bfd";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext137_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext137__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext137__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext137__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext137__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext137__hiz_depth_test_ambig_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext137_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext138_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext138_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext138";
    metric_set->symbol_name = "Ext138";
    metric_set->hw_config_guid = "4a31afda-7a08-4d3d-91fd-138bae3eb836";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext138_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext138__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext138__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext138__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext138__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext138__hiz_depth_test_ambig_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext138_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext139_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext139_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext139";
    metric_set->symbol_name = "Ext139";
    metric_set->hw_config_guid = "c800871b-2505-40f3-99e2-6c0ccb9102f2";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext139_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext139__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext139__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext139__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext139__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext139__hiz_depth_test_ambig_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext139_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext140_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext140_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext140";
    metric_set->symbol_name = "Ext140";
    metric_set->hw_config_guid = "067cbc21-6b6c-48c6-b47c-922a27b60b30";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext140_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext140__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext140__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext140__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext140__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext140__hiz_depth_test_ambig_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext140_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext141_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext141_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext141";
    metric_set->symbol_name = "Ext141";
    metric_set->hw_config_guid = "e8ee8621-7110-4d70-9651-846fd4fa3c3c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext141_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext141__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext141__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext141__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext141__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext141__hiz_depth_test_ambig_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext141_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext142_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext142_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext142";
    metric_set->symbol_name = "Ext142";
    metric_set->hw_config_guid = "87a9d5f2-2029-48b9-bbd3-78867e022166";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext142_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext142__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext142__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext142__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext142__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext142__hiz_depth_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext142_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext143_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext143_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext143";
    metric_set->symbol_name = "Ext143";
    metric_set->hw_config_guid = "bffa2382-3aff-471a-92af-5dd571c7868f";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext143_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext143__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext143__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext143__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext143__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext143__hiz_depth_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext143_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext144_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext144_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext144";
    metric_set->symbol_name = "Ext144";
    metric_set->hw_config_guid = "951f3ee4-6a3c-470c-b403-c01ee6a7e97d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext144_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext144__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext144__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext144__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext144__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext144__hiz_depth_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext144_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext145_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext145_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext145";
    metric_set->symbol_name = "Ext145";
    metric_set->hw_config_guid = "4d34c592-973b-4e75-a451-cf4ad90f79e1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext145_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext145__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext145__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext145__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext145__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext145__hiz_depth_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext145_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext146_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext146_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext146";
    metric_set->symbol_name = "Ext146";
    metric_set->hw_config_guid = "4a881a06-44b8-4199-a609-e0e4e22631c4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext146_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext146__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext146__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext146__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext146__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext146__hiz_depth_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext146_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext147_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext147_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext147";
    metric_set->symbol_name = "Ext147";
    metric_set->hw_config_guid = "20b339b5-abb6-48fc-8a09-bb4cafacbb72";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext147_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext147__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext147__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext147__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext147__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext147__hiz_depth_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext147_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext148_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext148_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext148";
    metric_set->symbol_name = "Ext148";
    metric_set->hw_config_guid = "8b62b22b-a467-4638-a113-81a5c59d64e8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext148_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext148__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext148__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext148__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext148__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext148__hiz_depth_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext148_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext149_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext149_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext149";
    metric_set->symbol_name = "Ext149";
    metric_set->hw_config_guid = "a563237d-76f3-45bc-82d7-c4a441c9230c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext149_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext149__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext149__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext149__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext149__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext149__hiz_depth_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext149_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext150_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext150_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext150";
    metric_set->symbol_name = "Ext150";
    metric_set->hw_config_guid = "dee6b408-d907-4eae-a961-7262816be56c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext150_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext150__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext150__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext150__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext150__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE0",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext150__hiz_depth_test_pass_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext150_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext151_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext151_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext151";
    metric_set->symbol_name = "Ext151";
    metric_set->hw_config_guid = "c2bf9d7d-0998-483b-bede-7ced3f8cf423";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext151_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext151__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext151__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext151__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext151__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE1",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext151__hiz_depth_test_pass_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext151_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext152_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext152_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext152";
    metric_set->symbol_name = "Ext152";
    metric_set->hw_config_guid = "06c6ecdb-9b66-400b-83ca-484309fba532";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext152_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext152__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext152__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext152__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext152__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE2",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext152__hiz_depth_test_pass_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext152_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext153_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext153_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext153";
    metric_set->symbol_name = "Ext153";
    metric_set->hw_config_guid = "af12ca37-4f11-4c7a-b6b3-695210972c92";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext153_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext153__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext153__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext153__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext153__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE3",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext153__hiz_depth_test_pass_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "DepthPipe",
                .availability = acmgt1_ext153_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext154_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext154";
    metric_set->symbol_name = "Ext154";
    metric_set->hw_config_guid = "f72930f8-79c3-49f3-9fa3-07a05070d1fd";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext154_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext154__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext154__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext154__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext154__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__hiz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE0",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE0",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_output_ready_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE0_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE1",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE1",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_output_ready_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE1_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE2",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE2",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_output_ready_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE2_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE3",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE3",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_output_ready_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_OUTPUT_READY_ZPIPE3_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext154__iz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "DepthPipe",
                .availability = acmgt1_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}


static void
acmgt1_add_ext155_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext155";
    metric_set->symbol_name = "Ext155";
    metric_set->hw_config_guid = "ac5346ae-2be4-47d1-8300-6e25c445297d";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext155_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext155__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext155__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS0",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext155__command_parser_compute_engine_busy_ccs0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS1",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS1",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext155__command_parser_compute_engine_busy_ccs1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS2",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS2",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext155__command_parser_compute_engine_busy_ccs2__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS3",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS3",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext155__command_parser_compute_engine_busy_ccs3__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the 3D queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext155__command_parser_render_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext155__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext155__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}


static void
acmgt1_add_ext156_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext156";
    metric_set->symbol_name = "Ext156";
    metric_set->hw_config_guid = "f8f7091d-7f71-42cf-84de-8ad23fe45432";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext156_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext156__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext156__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS0",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS1",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS1",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS2",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS2",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS3",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS3",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER FLUSH COUNT",
                .symbol_name = "COMMAND_PARSER_FLUSH_COUNT",
                .desc = "Number of Stalling flushes at the top of the pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext156__command_parser_flush_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DISPATCH_KERNEL_COUNT",
                .desc = "Number of compute walker commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext156__command_parser_render_engine_dispatch_kernel_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DRAW COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DRAW_COUNT",
                .desc = "Number of DRAW and MESH commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext156__command_parser_render_engine_draw_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext156__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext156__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
acmgt1_add_ext157_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext157";
    metric_set->symbol_name = "Ext157";
    metric_set->hw_config_guid = "ac6eecdc-0074-4a94-9269-48b5e3833439";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext157_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext157__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext157__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COPY ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_COPY_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the copy queue.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext157__command_parser_copy_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY VDBOX0",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX0",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext157__command_parser_video_engine_busy_vdbox0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENGINE BUSY VDBOX1",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENGINE_BUSY_VDBOX1",
                .desc = "Percentage of time in which there is a context loaded and active on the media queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext157__command_parser_video_engine_busy_vdbox1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX0",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX0",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext157__command_parser_video_enhancement_engine_busy_vebox0__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "COMMAND PARSER VIDEO ENHANCEMENT ENGINE BUSY VEBOX1",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE_BUSY_VEBOX1",
                .desc = "Percentage of time in which there is a context loaded and active on the video enhancement queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext157__command_parser_video_enhancement_engine_busy_vebox1__read,
                .max_float = percentage_max_callback_float,
                .group = "FrontEnd",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext157__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext157__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext158_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext158";
    metric_set->symbol_name = "Ext158";
    metric_set->hw_config_guid = "4c27f089-06ab-4c33-b084-fc7cc9cc78ea";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext158_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext158__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext158__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext158__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext158__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE0",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE0",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE1",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE1",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE2",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE2",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE3",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE3",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE4",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE4",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE5",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE5",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE6",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE6",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE7",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE7",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_input_message_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL INPUT RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7",
                .desc = "Number of Ray Tracing Traversal input rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext158__rt_traversal_input_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext158_RT_TRAVERSAL_INPUT_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext159_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext159";
    metric_set->symbol_name = "Ext159";
    metric_set->hw_config_guid = "1918a5b9-f991-4451-afff-565a739dbfb9";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext159_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext159__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext159__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext159__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext159__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext160_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext160";
    metric_set->symbol_name = "Ext160";
    metric_set->hw_config_guid = "6cf8ce0d-617c-4ed8-962c-6b750c0cf012";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext160_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext160__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext160__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext160__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext160__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext160__rt_closest_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext161_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext161";
    metric_set->symbol_name = "Ext161";
    metric_set->hw_config_guid = "453d205a-8bd1-4ebe-b617-1168cbfda3ca";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext161_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext161__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext161__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext161__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext161__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext161__rt_miss_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext162_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext162";
    metric_set->symbol_name = "Ext162";
    metric_set->hw_config_guid = "9d94eefc-0c25-4725-a6af-3eb468cae42d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext162_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext162__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext162__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext162__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext162__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext162__rt_miss_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext163_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext163";
    metric_set->symbol_name = "Ext163";
    metric_set->hw_config_guid = "fbba6a19-98df-4a94-9a42-2660674d8e25";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext163_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext163__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext163__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext163__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext163__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext164_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext164";
    metric_set->symbol_name = "Ext164";
    metric_set->hw_config_guid = "ec971ed3-3fb2-4d4c-bf27-08eeb418dc68";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext164_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext164__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext164__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext164__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext164__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext164__rt_any_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext165_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext165";
    metric_set->symbol_name = "Ext165";
    metric_set->hw_config_guid = "a1d6b535-1d00-4951-bdcc-8586b9ba7c0a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext165_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext165__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext165__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext165__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext165__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext165__rt_intersection_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext166_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext166";
    metric_set->symbol_name = "Ext166";
    metric_set->hw_config_guid = "5f78bfe9-b17b-4df2-b1de-54e7c84d93ab";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext166_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext166__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext166__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext166__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext166__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext166__rt_intersection_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext167_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext167";
    metric_set->symbol_name = "Ext167";
    metric_set->hw_config_guid = "c76128ab-fe65-4ccc-94ea-f351ccbd5f16";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext167_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext167__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext167__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext167__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext167__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext167__rt_callable_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext168_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext168";
    metric_set->symbol_name = "Ext168";
    metric_set->hw_config_guid = "fac0445a-ae46-412e-bf26-0b4dddd64485";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext168_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext168__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext168__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext168__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext168__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext168__rt_callable_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext169_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext169";
    metric_set->symbol_name = "Ext169";
    metric_set->hw_config_guid = "386322a7-4cf5-4bf9-bbd9-35a6477a4479";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext169_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext169__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext169__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext169__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext169__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext169__rt_traversal_output_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext169__rt_traversal_output_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext169__rt_traversal_output_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext169__rt_traversal_output_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext170_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext170";
    metric_set->symbol_name = "Ext170";
    metric_set->hw_config_guid = "b175ecb9-b8cd-4f9c-97d4-73bf5cf12fa7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext170_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext170__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext170__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext170__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext170__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext170__rt_traversal_output_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext170__rt_traversal_output_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext170__rt_traversal_output_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext170__rt_traversal_output_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext171_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext171";
    metric_set->symbol_name = "Ext171";
    metric_set->hw_config_guid = "f2b8f05e-1936-47b6-b1ac-99a441971cea";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext171_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext171__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext171__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext171__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext171__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE0",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE1",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE2",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE3",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE4",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE5",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE6",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE7",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_quad_test_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE0",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE0",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE1",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE1",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE2",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE2",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE3",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE3",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE4",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE4",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE5",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE5",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE6",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE6",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE7",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE7",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext171__rt_transform_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext171_RT_TRANSFORM_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext172_RT_REQUEST_COLLISION_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext172_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext172";
    metric_set->symbol_name = "Ext172";
    metric_set->hw_config_guid = "72ae9945-8887-4c8b-acd6-559e4b92203e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext172_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext172__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext172__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext172__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext172__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE0",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE0",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE0_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE1",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE1",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE1_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE2",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE2",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE2_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE3",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE3",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE3_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE4",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE4",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE4_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE5",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE5",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE5_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE6",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE6",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE6_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE7",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE7",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext172__rt_message_stall_count_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_MESSAGE_STALL_COUNT_XECORE7_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE0",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE0",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE0_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE1",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE1",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE1_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE2",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE2",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE2_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE3",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE3",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE3_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE4",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE4",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE4_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE5",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE5",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE5_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE6",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE6",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE6_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE7",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE7",
                .desc = "Percentage of time in which  Ray Tracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext172__rt_request_collision_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext172_RT_REQUEST_COLLISION_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext173_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext173_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext173_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext173_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext173_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext173_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext173_XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext173_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext173";
    metric_set->symbol_name = "Ext173";
    metric_set->hw_config_guid = "1861b4c1-3950-4855-a8db-6e0b90fc44aa";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext173_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext173__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext173__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext173__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext173__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext173_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext173_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext173__xve_stall_barrier_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext173_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext173_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext173__xve_stall_other_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext173_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext173__xve_stall_sbid_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext173_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext173__xve_stall_sendwr_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext173_XVE_STALL_SENDWR_XECORE0_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext174_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext174_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext174_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext174_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext174_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext174_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext174_XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext174_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext174";
    metric_set->symbol_name = "Ext174";
    metric_set->hw_config_guid = "b29accb6-ff91-45d5-953b-2ca3c0983f66";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext174_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext174__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext174__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext174__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext174__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext174_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext174_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext174__xve_stall_barrier_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext174_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext174_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext174__xve_stall_other_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext174_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext174__xve_stall_sbid_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext174_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext174__xve_stall_sendwr_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext174_XVE_STALL_SENDWR_XECORE1_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext175_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext175_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext175_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext175_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext175_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext175_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext175_XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext175_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext175";
    metric_set->symbol_name = "Ext175";
    metric_set->hw_config_guid = "218c081a-6fe6-4a26-afb6-ca6bd1bf78eb";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext175_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext175__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext175__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext175__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext175__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext175_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext175_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext175__xve_stall_barrier_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext175_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext175_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext175__xve_stall_other_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext175_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext175__xve_stall_sbid_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext175_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext175__xve_stall_sendwr_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext175_XVE_STALL_SENDWR_XECORE2_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext176_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext176_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext176_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext176_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext176_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext176_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext176_XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext176_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext176";
    metric_set->symbol_name = "Ext176";
    metric_set->hw_config_guid = "f7d99e5e-4cb7-47da-835f-ec31a8838dc5";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext176_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext176__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext176__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext176__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext176__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext176_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext176_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext176__xve_stall_barrier_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext176_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext176_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext176__xve_stall_other_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext176_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext176__xve_stall_sbid_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext176_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext176__xve_stall_sendwr_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext176_XVE_STALL_SENDWR_XECORE3_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext177_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext177_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext177_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext177_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext177_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext177_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext177_XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext177_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext177";
    metric_set->symbol_name = "Ext177";
    metric_set->hw_config_guid = "da0fd1f5-25bd-44d7-aced-87d78f3f0a7d";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext177_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext177__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext177__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext177__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext177__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext177__xve_shared_function_access_hold_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext177_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext177__xve_stall_aluwr_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext177_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext177__xve_stall_barrier_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext177_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext177__xve_stall_instfetch_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext177_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext177__xve_stall_other_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext177_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext177__xve_stall_sbid_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext177_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext177__xve_stall_sendwr_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext177_XVE_STALL_SENDWR_XECORE4_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext178_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext178_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext178_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext178_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext178_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext178_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext178_XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext178_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext178";
    metric_set->symbol_name = "Ext178";
    metric_set->hw_config_guid = "e1495a70-d6ea-4867-aa48-4135567bf19b";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext178_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext178__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext178__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext178__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext178__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext178__xve_shared_function_access_hold_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext178_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext178__xve_stall_aluwr_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext178_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext178__xve_stall_barrier_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext178_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext178__xve_stall_instfetch_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext178_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext178__xve_stall_other_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext178_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext178__xve_stall_sbid_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext178_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext178__xve_stall_sendwr_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext178_XVE_STALL_SENDWR_XECORE5_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext179_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext179_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext179_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext179_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext179_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext179_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext179_XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext179_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext179";
    metric_set->symbol_name = "Ext179";
    metric_set->hw_config_guid = "d2b946b8-ddbc-47bb-b02d-f89652163b6a";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext179_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext179__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext179__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext179__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext179__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext179__xve_shared_function_access_hold_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext179_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext179__xve_stall_aluwr_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext179_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext179__xve_stall_barrier_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext179_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext179__xve_stall_instfetch_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext179_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext179__xve_stall_other_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext179_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext179__xve_stall_sbid_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext179_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext179__xve_stall_sendwr_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext179_XVE_STALL_SENDWR_XECORE6_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext180_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext180_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext180_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext180_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext180_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext180_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext180_XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext180_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext180";
    metric_set->symbol_name = "Ext180";
    metric_set->hw_config_guid = "44915f22-aaca-4871-b8ca-7a83aa83d605";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext180_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext180__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext180__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext180__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext180__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext180__xve_shared_function_access_hold_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext180_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext180__xve_stall_aluwr_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext180_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext180__xve_stall_barrier_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext180_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext180__xve_stall_instfetch_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext180_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext180__xve_stall_other_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext180_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext180__xve_stall_sbid_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext180_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SENDWR XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for SEND to write GRF register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext180__xve_stall_sendwr_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext180_XVE_STALL_SENDWR_XECORE7_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool acmgt1_ext181_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext181_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext181_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext181_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext181";
    metric_set->symbol_name = "Ext181";
    metric_set->hw_config_guid = "fe0eda19-22d8-410e-b61d-24bce297d8ae";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext181_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext181__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext181__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext181__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext181__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE0 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE0_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext181__xve_inst_issued_all_xecore0_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext181_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE1 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE1_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext181__xve_inst_issued_all_xecore1_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext181_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE2 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE2_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext181__xve_inst_issued_all_xecore2_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext181_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext182_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext182_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext182_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext182_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext182";
    metric_set->symbol_name = "Ext182";
    metric_set->hw_config_guid = "aef5adcb-e3ef-4839-aea5-a6bbb9bb5faa";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext182_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext182__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext182__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext182__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext182__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE3 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE3_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext182__xve_inst_issued_all_xecore3_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext182_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE4 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE4_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext182__xve_inst_issued_all_xecore4_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext182_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE5 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE5_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext182__xve_inst_issued_all_xecore5_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext182_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext183_RENDER_CACHE_ALLOC_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext183_RENDER_CACHE_ALLOC_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext183_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext183_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext183_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext183";
    metric_set->symbol_name = "Ext183";
    metric_set->hw_config_guid = "1cf7ed05-8260-4abe-b00c-7f3ae3441d4b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext183_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext183__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext183__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext183__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext183__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE0",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE0",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext183__render_cache_alloc_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext183_RENDER_CACHE_ALLOC_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE1",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE1",
                .desc = "Number of Render Cache allocations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext183__render_cache_alloc_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext183_RENDER_CACHE_ALLOC_L3NODE1_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE6 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE6_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext183__xve_inst_issued_all_xecore6_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext183_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE7 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE7_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext183__xve_inst_issued_all_xecore7_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext183_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext184_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext184_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext184_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext184";
    metric_set->symbol_name = "Ext184";
    metric_set->hw_config_guid = "39badcb4-5410-4218-b272-1e5edc606b5c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext184_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext184__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext184__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext184__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext184__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext184__rt_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext184_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext184__rt_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext184_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext185_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext185";
    metric_set->symbol_name = "Ext185";
    metric_set->hw_config_guid = "e1e40930-36f2-480c-b15d-cf2fb07f18e1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext185_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext185__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext185__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext185__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext185__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext185__rt_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext185__rt_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext186_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext186";
    metric_set->symbol_name = "Ext186";
    metric_set->hw_config_guid = "4edf8144-d144-4110-b34c-0f6133409bae";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext186_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext186__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext186__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext186__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext186__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext186__rt_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext186__rt_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext187_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext187_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext187_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext187";
    metric_set->symbol_name = "Ext187";
    metric_set->hw_config_guid = "a035c742-180e-4bf0-8009-5668cb08981f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext187_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext187__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext187__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext187__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext187__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext187__rt_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext187_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext187__rt_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext187_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext188_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext188";
    metric_set->symbol_name = "Ext188";
    metric_set->hw_config_guid = "1236f8d6-fa44-40eb-addc-8e4695b02ab3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext188_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext188__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext188__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext188__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext188__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext188__rt_load_store_cache_write_from_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext188__rt_load_store_cache_write_from_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext189_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext189";
    metric_set->symbol_name = "Ext189";
    metric_set->hw_config_guid = "d37f51e7-16dd-4616-88a0-cfc54b90a43f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext189_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext189__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext189__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext189__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext189__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext189__rt_load_store_cache_write_from_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext189__rt_load_store_cache_write_from_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext190_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext190_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext190_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext190";
    metric_set->symbol_name = "Ext190";
    metric_set->hw_config_guid = "c9ac09ca-af08-4072-8e8b-dbc81cd95ada";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext190_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext190__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext190__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext190__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext190__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext190__rt_load_store_cache_write_from_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext190_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext190__rt_load_store_cache_write_from_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext190_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext191_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext191_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext191_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext191";
    metric_set->symbol_name = "Ext191";
    metric_set->hw_config_guid = "9e1699e6-cea6-46de-bb89-050415f0a8a2";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext191_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext191__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext191__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext191__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext191__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext191__rt_load_store_cache_write_from_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext191_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext191__rt_load_store_cache_write_from_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext191_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext192_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext192";
    metric_set->symbol_name = "Ext192";
    metric_set->hw_config_guid = "e671dd75-968d-49e4-9c03-5269d95de66e";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext192_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext192__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext192__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext192__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext192__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE0",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE1",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE2",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE3",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE4",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE5",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE6",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE7",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext192__rt_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "RayTracing",
                .availability = acmgt1_ext192_RT_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext193_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext193_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext193_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext193";
    metric_set->symbol_name = "Ext193";
    metric_set->hw_config_guid = "9a53799a-f746-4d6d-a723-57af53243454";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext193_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext193__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext193__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext193__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext193__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext193__pixel_post_process_input_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext193_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext193__pixel_post_process_input_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext193_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext194_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext194_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext194_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext194";
    metric_set->symbol_name = "Ext194";
    metric_set->hw_config_guid = "3b4157d9-9905-48c5-a9fa-3f53f94b9b5d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext194_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext194__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext194__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext194__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext194__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext194__pixel_post_process_input_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext194_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext194__pixel_post_process_input_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext194_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext195_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext195";
    metric_set->symbol_name = "Ext195";
    metric_set->hw_config_guid = "b7468d66-8862-4deb-aeb7-d2cefa81ea0e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext195_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext195__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext195__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext195__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext195__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext195__xve_multiple_pipe_active_xecore0_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext195__xve_multiple_pipe_active_xecore1_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext195__xve_multiple_pipe_active_xecore2_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext195__xve_multiple_pipe_active_xecore3_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext196_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext196";
    metric_set->symbol_name = "Ext196";
    metric_set->hw_config_guid = "a09b78bb-b10e-4250-84c5-336f839c4e0c";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext196_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext196__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext196__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext196__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext196__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext196__xve_multiple_pipe_active_xecore4_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext196__xve_multiple_pipe_active_xecore5_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext196__xve_multiple_pipe_active_xecore6_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext196__xve_multiple_pipe_active_xecore7_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
                .availability = acmgt1_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext197_GPGPU_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext197_GPGPU_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext197_GPGPU_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext197_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext197";
    metric_set->symbol_name = "Ext197";
    metric_set->hw_config_guid = "8b7e5a75-7734-4d48-bdd7-0adf976b8a89";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext197_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext197__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext197__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE0",
                .symbol_name = "GPGPU_DISPATCH_XECORE0",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext197__gpgpu_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext197_GPGPU_DISPATCH_XECORE0_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE1",
                .symbol_name = "GPGPU_DISPATCH_XECORE1",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext197__gpgpu_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext197_GPGPU_DISPATCH_XECORE1_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE2",
                .symbol_name = "GPGPU_DISPATCH_XECORE2",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext197__gpgpu_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext197_GPGPU_DISPATCH_XECORE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext197__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext197__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext198_GPGPU_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext198_GPGPU_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext198_GPGPU_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext198_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext198";
    metric_set->symbol_name = "Ext198";
    metric_set->hw_config_guid = "8157717a-d7e3-465e-a6b9-a5a5d4902b49";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext198_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext198__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext198__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE3",
                .symbol_name = "GPGPU_DISPATCH_XECORE3",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext198__gpgpu_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext198_GPGPU_DISPATCH_XECORE3_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE4",
                .symbol_name = "GPGPU_DISPATCH_XECORE4",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext198__gpgpu_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext198_GPGPU_DISPATCH_XECORE4_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE5",
                .symbol_name = "GPGPU_DISPATCH_XECORE5",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext198__gpgpu_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext198_GPGPU_DISPATCH_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext198__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext198__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext199_GPGPU_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext199_GPGPU_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext199_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext199";
    metric_set->symbol_name = "Ext199";
    metric_set->hw_config_guid = "fc122f7d-c66a-458b-a06c-cee29569262d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext199_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext199__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext199__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE6",
                .symbol_name = "GPGPU_DISPATCH_XECORE6",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext199__gpgpu_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext199_GPGPU_DISPATCH_XECORE6_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE7",
                .symbol_name = "GPGPU_DISPATCH_XECORE7",
                .desc = "Percentage of time spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext199__gpgpu_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ThreadDispatcher",
                .availability = acmgt1_ext199_GPGPU_DISPATCH_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext199__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext199__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext200_SLM_ACCESS_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext200_SLM_ACCESS_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext200_SLM_ACCESS_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext200_SLM_ACCESS_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext200_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext200";
    metric_set->symbol_name = "Ext200";
    metric_set->hw_config_guid = "80da4065-1cc6-4e17-8594-731e1acc01ef";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext200_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext200__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext200__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext200__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext200__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE0",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE0",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext200__slm_access_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext200_SLM_ACCESS_COUNT_XECORE0_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE1",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE1",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext200__slm_access_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext200_SLM_ACCESS_COUNT_XECORE1_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE2",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE2",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext200__slm_access_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext200_SLM_ACCESS_COUNT_XECORE2_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE3",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE3",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext200__slm_access_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext200_SLM_ACCESS_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext201_SLM_ACCESS_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext201_SLM_ACCESS_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext201_SLM_ACCESS_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext201_SLM_ACCESS_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext201_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext201";
    metric_set->symbol_name = "Ext201";
    metric_set->hw_config_guid = "5c664618-1692-4ded-b6bb-a9e17f37250d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext201_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext201__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext201__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext201__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext201__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT XECORE4",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE4",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext201__slm_access_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext201_SLM_ACCESS_COUNT_XECORE4_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE5",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE5",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext201__slm_access_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext201_SLM_ACCESS_COUNT_XECORE5_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE6",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE6",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext201__slm_access_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext201_SLM_ACCESS_COUNT_XECORE6_availability,
            },

            {
                .name = "SLM ACCESS COUNT XECORE7",
                .symbol_name = "SLM_ACCESS_COUNT_XECORE7",
                .desc = "Number of SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext201__slm_access_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext201_SLM_ACCESS_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}


static void
acmgt1_add_ext202_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext202";
    metric_set->symbol_name = "Ext202";
    metric_set->hw_config_guid = "671c0d10-0f02-490f-acf6-2d2a88c0bc62";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext202_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext202__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext202__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext202__gpu_memory_l3_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext202__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext202__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt1_add_ext203_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext203";
    metric_set->symbol_name = "Ext203";
    metric_set->hw_config_guid = "d1c46c3e-fd18-4ca4-905b-64b95a6f10e8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext203_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext203__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext203__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext203__gpu_memory_l3_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext203__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext203__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext204_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext204_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext204_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext204";
    metric_set->symbol_name = "Ext204";
    metric_set->hw_config_guid = "4e426fcb-9591-42a4-9b9a-7207d548bc0b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext204_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext204__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext204__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext204__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext204__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext204__rt_instance_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext204_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext204__rt_internal_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext204__rt_traversal_step_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext204_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext205_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext205_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext205_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext205";
    metric_set->symbol_name = "Ext205";
    metric_set->hw_config_guid = "12aa9868-f7c6-4c8d-80fe-cc1605608ef1";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext205_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext205__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext205__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext205__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext205__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext205__rt_instance_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext205__rt_internal_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext205_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext205__rt_traversal_step_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext205_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext206_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext206_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext206_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext206";
    metric_set->symbol_name = "Ext206";
    metric_set->hw_config_guid = "7a64382c-70d1-41c4-a1e9-28a8bcb4785a";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext206_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext206__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext206__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext206__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext206__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext206__rt_instance_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext206_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext206__rt_internal_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext206__rt_traversal_step_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext206_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext207_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext207_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext207_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext207";
    metric_set->symbol_name = "Ext207";
    metric_set->hw_config_guid = "2fa63ea7-c2d9-40fc-b9d5-74cf4a7a3761";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext207_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext207__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext207__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext207__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext207__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext207__rt_instance_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext207__rt_internal_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext207_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext207__rt_traversal_step_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext207_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext208_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext208_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext208_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext208_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext208";
    metric_set->symbol_name = "Ext208";
    metric_set->hw_config_guid = "c26befd3-0199-4b5a-9768-963eded47ddc";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext208_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext208__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext208__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext208__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext208__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext208__rt_instance_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext208_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext208__rt_internal_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext208_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext208__rt_traversal_step_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext208_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext209_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext209_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext209_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext209_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext209";
    metric_set->symbol_name = "Ext209";
    metric_set->hw_config_guid = "6ac62a5e-3593-4f68-90c1-452cbc83af7b";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext209_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext209__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext209__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext209__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext209__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext209__rt_instance_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext209_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext209__rt_internal_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext209_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext209__rt_traversal_step_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext209_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext210_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext210_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext210_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext210_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext210";
    metric_set->symbol_name = "Ext210";
    metric_set->hw_config_guid = "869238af-0548-47ba-9703-fb4d12825f89";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext210_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext210__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext210__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext210__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext210__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext210__rt_instance_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext210_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext210__rt_internal_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext210_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext210__rt_traversal_step_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext210_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext211_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext211_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext211_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext211_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext211";
    metric_set->symbol_name = "Ext211";
    metric_set->hw_config_guid = "1986e401-2a47-4ced-be1e-1412f795388f";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext211_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext211__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext211__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext211__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext211__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext211__rt_instance_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext211_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext211__rt_internal_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext211_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext211__rt_traversal_step_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext211_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool acmgt1_ext212_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext212_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext212_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext212";
    metric_set->symbol_name = "Ext212";
    metric_set->hw_config_guid = "61f0e78f-0095-4595-993c-0d2a7b474f05";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext212_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext212__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext212__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext212__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext212__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext212__rt_procedural_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext212_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE0",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext212__rt_quad_leaf_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext212_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext213_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext213_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext213_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext213";
    metric_set->symbol_name = "Ext213";
    metric_set->hw_config_guid = "aac878c4-c131-4e46-a022-673b0c0f6adf";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext213_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext213__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext213__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext213__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext213__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext213__rt_procedural_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext213_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE1",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext213__rt_quad_leaf_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext213_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext214_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext214_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext214_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext214";
    metric_set->symbol_name = "Ext214";
    metric_set->hw_config_guid = "02fc686b-6061-4224-957b-0c80f4fb5973";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext214_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext214__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext214__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext214__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext214__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext214__rt_procedural_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext214_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE2",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext214__rt_quad_leaf_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext214_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext215_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext215_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext215_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext215";
    metric_set->symbol_name = "Ext215";
    metric_set->hw_config_guid = "6965f87c-43a9-437b-9bfb-78e30f504806";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext215_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext215__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext215__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext215__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext215__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext215__rt_procedural_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext215_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE3",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext215__rt_quad_leaf_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext215_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext216_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext216_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext216_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext216";
    metric_set->symbol_name = "Ext216";
    metric_set->hw_config_guid = "834f9ddb-0ef2-47a8-bcf3-871cf2b5634e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext216_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext216__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext216__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext216__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext216__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext216__rt_procedural_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext216_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE4",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext216__rt_quad_leaf_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext216_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext217_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext217_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext217_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext217";
    metric_set->symbol_name = "Ext217";
    metric_set->hw_config_guid = "dd1c62fd-8d41-4f1d-a980-95eba5b62d3d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext217_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext217__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext217__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext217__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext217__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext217__rt_procedural_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext217_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE5",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext217__rt_quad_leaf_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext217_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext218_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext218_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext218_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext218";
    metric_set->symbol_name = "Ext218";
    metric_set->hw_config_guid = "1a1e9195-858b-47aa-8f1c-c66eea6efbb9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext218_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext218__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext218__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext218__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext218__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext218__rt_procedural_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext218_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE6",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext218__rt_quad_leaf_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext218_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext219_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext219_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext219_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext219";
    metric_set->symbol_name = "Ext219";
    metric_set->hw_config_guid = "a75e98da-d723-42d0-8cd2-c4dc704e6aa1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext219_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext219__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext219__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext219__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext219__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext219__rt_procedural_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext219_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE7",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext219__rt_quad_leaf_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext219_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext220_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext220";
    metric_set->symbol_name = "Ext220";
    metric_set->hw_config_guid = "440ba901-38f7-495d-986b-486534274741";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext220_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext220__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext220__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext220__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext220__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE0",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE0",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext220__rt_bvh_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE1",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE1",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext220__rt_bvh_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE2",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE2",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext220__rt_bvh_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE3",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE3",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext220__rt_bvh_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext220_RT_BVH_CACHE_MISS_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext221_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext221";
    metric_set->symbol_name = "Ext221";
    metric_set->hw_config_guid = "6d047d05-95ca-46b4-aac3-a7b055b8fd15";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext221_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext221__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext221__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext221__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext221__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE4",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE4",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext221__rt_bvh_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE5",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE5",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext221__rt_bvh_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE6",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE6",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext221__rt_bvh_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE7",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE7",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext221__rt_bvh_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "RayTracing",
                .availability = acmgt1_ext221_RT_BVH_CACHE_MISS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext222_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext222";
    metric_set->symbol_name = "Ext222";
    metric_set->hw_config_guid = "a338ef12-c1bf-45f8-8c0b-084fa99376c8";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext222_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext222__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext222__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext222__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext222__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext222__load_store_cache_number_of_bank_access_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext222_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext223_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext223";
    metric_set->symbol_name = "Ext223";
    metric_set->hw_config_guid = "2684ee0f-2950-4445-939a-549f07d3370a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext223_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext223__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext223__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext223__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext223__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE NUMBER OF BANK ACCESS COUNT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7",
                .desc = "Number of Load Store Cache banks accessed in a clock.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext223__load_store_cache_number_of_bank_access_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext223_LOAD_STORE_CACHE_NUMBER_OF_BANK_ACCESS_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool acmgt1_ext224_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext224_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext224_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext224";
    metric_set->symbol_name = "Ext224";
    metric_set->hw_config_guid = "e1de83dc-4fb2-4e1a-852d-9c5e49bf45db";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext224_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext224__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext224__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext224__color_pipe_cache_latency2_stall_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext224_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext224__color_pipe_cache_latency2_stall_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "ColorPipe",
                .availability = acmgt1_ext224_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext224__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext224__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext225_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext225_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext225";
    metric_set->symbol_name = "Ext225";
    metric_set->hw_config_guid = "81beafd2-8d1e-46bc-96c0-7f914522a760";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext225_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext225__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext225__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext225__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext225__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext225_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext226_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext226_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext226";
    metric_set->symbol_name = "Ext226";
    metric_set->hw_config_guid = "e299ef7e-7be1-4554-a5c7-e64d36be98e6";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext226_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext226__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext226__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext226__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext226__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext226__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext226_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext227_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext227_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext227";
    metric_set->symbol_name = "Ext227";
    metric_set->hw_config_guid = "e9d1019b-205c-4d1e-a2a7-fd7708a6ad91";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext227_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext227__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext227__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext227__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext227__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext227_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext228_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext228_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext228";
    metric_set->symbol_name = "Ext228";
    metric_set->hw_config_guid = "ccf8706c-40ea-40a6-ab4c-47e5b32a1485";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext228_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext228__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext228__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext228__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext228__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext228__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
                .availability = acmgt1_ext228_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext229_SLM_BANK_CONFLICT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext229_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext229";
    metric_set->symbol_name = "Ext229";
    metric_set->hw_config_guid = "2ebb4747-7eb7-4a65-96f8-6a57131a5e82";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext229_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext229__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext229__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext229__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext229__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE0",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE0",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext229__slm_bank_conflict_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext229_SLM_BANK_CONFLICT_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext230_SLM_BANK_CONFLICT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext230_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext230";
    metric_set->symbol_name = "Ext230";
    metric_set->hw_config_guid = "baaa8d7e-40b7-4abd-991a-d71265437230";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext230_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext230__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext230__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext230__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext230__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE1",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE1",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext230__slm_bank_conflict_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext230_SLM_BANK_CONFLICT_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext231_SLM_BANK_CONFLICT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext231_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext231";
    metric_set->symbol_name = "Ext231";
    metric_set->hw_config_guid = "a57ee736-e6ab-4e8b-a719-3a63d7d20f34";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext231_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext231__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext231__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext231__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext231__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE2",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE2",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext231__slm_bank_conflict_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext231_SLM_BANK_CONFLICT_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext232_SLM_BANK_CONFLICT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext232_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext232";
    metric_set->symbol_name = "Ext232";
    metric_set->hw_config_guid = "c33082a0-ae0d-4679-adbc-9566c75ffe6a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext232_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext232__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext232__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext232__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext232__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE3",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE3",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext232__slm_bank_conflict_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext232_SLM_BANK_CONFLICT_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext233_SLM_BANK_CONFLICT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext233_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext233";
    metric_set->symbol_name = "Ext233";
    metric_set->hw_config_guid = "3381cf54-6e4f-48b1-81c9-d5cfd542d316";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext233_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext233__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext233__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext233__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext233__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE4",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE4",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext233__slm_bank_conflict_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext233_SLM_BANK_CONFLICT_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext234_SLM_BANK_CONFLICT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext234_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext234";
    metric_set->symbol_name = "Ext234";
    metric_set->hw_config_guid = "b7f1e445-7aaa-4fe3-a7f1-53fe57e1a7c8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext234_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext234__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext234__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext234__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext234__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE5",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE5",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext234__slm_bank_conflict_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext234_SLM_BANK_CONFLICT_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext235_SLM_BANK_CONFLICT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext235_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext235";
    metric_set->symbol_name = "Ext235";
    metric_set->hw_config_guid = "7e29d0d3-2ec5-4716-90d4-917c7b3cbdca";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext235_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext235__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext235__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext235__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext235__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE6",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE6",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext235__slm_bank_conflict_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext235_SLM_BANK_CONFLICT_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext236_SLM_BANK_CONFLICT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext236_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext236";
    metric_set->symbol_name = "Ext236";
    metric_set->hw_config_guid = "ae42189a-f2a1-4494-84b0-f2d506decbc1";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext236_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext236__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext236__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext236__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext236__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE7",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE7",
                .desc = "Number of SLM accesses resulting in a bank conflict.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext236__slm_bank_conflict_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext236_SLM_BANK_CONFLICT_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext237_L3_MISS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext237_L3_MISS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext237_L3_MISS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext237_L3_MISS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext237_L3_MISS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext237_L3_MISS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext237_L3_MISS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}
static bool acmgt1_ext237_L3_MISS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (1 * 2)))) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext237_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext237";
    metric_set->symbol_name = "Ext237";
    metric_set->hw_config_guid = "6f65878e-1b6b-4a3b-8107-837073903643";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext237_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext237__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext237__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext237__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext237__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 MISS L3BANK0",
                .symbol_name = "L3_MISS_L3BANK0",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK0_availability,
            },

            {
                .name = "L3 MISS L3BANK1",
                .symbol_name = "L3_MISS_L3BANK1",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK1_availability,
            },

            {
                .name = "L3 MISS L3BANK2",
                .symbol_name = "L3_MISS_L3BANK2",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK2_availability,
            },

            {
                .name = "L3 MISS L3BANK3",
                .symbol_name = "L3_MISS_L3BANK3",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK3_availability,
            },

            {
                .name = "L3 MISS L3BANK4",
                .symbol_name = "L3_MISS_L3BANK4",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK4_availability,
            },

            {
                .name = "L3 MISS L3BANK5",
                .symbol_name = "L3_MISS_L3BANK5",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK5_availability,
            },

            {
                .name = "L3 MISS L3BANK6",
                .symbol_name = "L3_MISS_L3BANK6",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK6_availability,
            },

            {
                .name = "L3 MISS L3BANK7",
                .symbol_name = "L3_MISS_L3BANK7",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext237__l3_miss_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3Cache",
                .availability = acmgt1_ext237_L3_MISS_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool acmgt1_ext238_AMFS_L3_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_AMFS_L3_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext238_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext238";
    metric_set->symbol_name = "Ext238";
    metric_set->hw_config_guid = "a1c8b5b0-7b8c-4dbc-a4dd-eb29f8055ab0";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext238_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 WRITE SLICE0",
                .symbol_name = "AMFS_L3_WRITE_SLICE0",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__amfs_l3_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext238_AMFS_L3_WRITE_SLICE0_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE1",
                .symbol_name = "AMFS_L3_WRITE_SLICE1",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__amfs_l3_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "AMFS",
                .availability = acmgt1_ext238_AMFS_L3_WRITE_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext238__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext238__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext238__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext238__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext238__xve_dataport_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Dataport",
                .availability = acmgt1_ext238_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}


static void
acmgt1_add_ext239_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext239";
    metric_set->symbol_name = "Ext239";
    metric_set->hw_config_guid = "cc574967-0ba6-4c22-801f-881b3974395a";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext239_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext239__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext239__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI0",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext239__gpu_memory_l3_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext239__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext239__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
acmgt1_add_ext240_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext240";
    metric_set->symbol_name = "Ext240";
    metric_set->hw_config_guid = "d96495d3-d734-4b58-bf54-ece1a4a1ab09";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext240_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext240__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext240__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI1",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext240__gpu_memory_l3_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Memory",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext240__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext240__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_HIT_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext500_ICACHE_MISS_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext500_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext500";
    metric_set->symbol_name = "Ext500";
    metric_set->hw_config_guid = "1c157760-179c-40d1-aa3c-b419f609ea79";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext500_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext500__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext500__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext500__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext500__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_hit_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_HIT_BANK0_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext500__icache_miss_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext500_ICACHE_MISS_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_HIT_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext501_ICACHE_MISS_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext501_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext501";
    metric_set->symbol_name = "Ext501";
    metric_set->hw_config_guid = "06451560-fa04-4f38-b502-e0a096965a64";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext501_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext501__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext501__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext501__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext501__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_hit_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_HIT_BANK1_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext501__icache_miss_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext501_ICACHE_MISS_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_HIT_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext502_ICACHE_MISS_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext502_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext502";
    metric_set->symbol_name = "Ext502";
    metric_set->hw_config_guid = "9d21c47c-92e0-4454-b3f1-484f27763e83";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext502_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext502__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext502__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext502__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext502__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_hit_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_HIT_BANK2_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext502__icache_miss_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext502_ICACHE_MISS_BANK2_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_HIT_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext503_ICACHE_MISS_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext503_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext503";
    metric_set->symbol_name = "Ext503";
    metric_set->hw_config_guid = "3cbb77d0-15f3-4bd0-8db1-5644266d78fc";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext503_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext503__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext503__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext503__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext503__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_hit_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_HIT_BANK3_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext503__icache_miss_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "VectorEngine",
                .availability = acmgt1_ext503_ICACHE_MISS_BANK3_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool acmgt1_ext508_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext508_SLM_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext508_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext508";
    metric_set->symbol_name = "Ext508";
    metric_set->hw_config_guid = "e81aaa56-a54b-491f-9803-ed19d2762e13";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext508_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext508__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext508__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext508__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext508__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext508__load_store_cache_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext508_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext508__slm_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext508_SLM_BYTE_READ_BANK0_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext509_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext509_SLM_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext509_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext509";
    metric_set->symbol_name = "Ext509";
    metric_set->hw_config_guid = "3c10260c-cb15-4474-ab84-c226d54f2974";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext509_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext509__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext509__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext509__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext509__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext509__load_store_cache_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext509_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext509__slm_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext509_SLM_BYTE_READ_BANK0_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext510_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext510_SLM_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext510_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext510";
    metric_set->symbol_name = "Ext510";
    metric_set->hw_config_guid = "95455b22-bda5-4f6e-86ae-0e500f0b419e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext510_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext510__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext510__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext510__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext510__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext510__load_store_cache_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext510_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext510__slm_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext510_SLM_BYTE_READ_BANK0_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext511_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext511_SLM_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext511_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext511";
    metric_set->symbol_name = "Ext511";
    metric_set->hw_config_guid = "95137f7b-f35e-4bef-9949-3c6681813bb9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext511_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext511__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext511__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext511__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext511__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext511__load_store_cache_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext511_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext511__slm_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext511_SLM_BYTE_READ_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext512_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext512_SLM_BYTE_READ_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext512_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext512";
    metric_set->symbol_name = "Ext512";
    metric_set->hw_config_guid = "3effc828-e8ca-4aab-a1a6-c478a41d55a7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext512_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext512__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext512__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext512__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext512__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext512__load_store_cache_byte_read_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext512_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE4",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE4",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext512__slm_byte_read_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext512_SLM_BYTE_READ_BANK0_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext513_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext513_SLM_BYTE_READ_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext513_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext513";
    metric_set->symbol_name = "Ext513";
    metric_set->hw_config_guid = "42d607af-0d8c-4d80-8443-73f5952060bb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext513_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext513__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext513__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext513__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext513__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext513__load_store_cache_byte_read_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext513_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE5",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE5",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext513__slm_byte_read_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext513_SLM_BYTE_READ_BANK0_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext514_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext514_SLM_BYTE_READ_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext514_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext514";
    metric_set->symbol_name = "Ext514";
    metric_set->hw_config_guid = "bc6702b9-80d9-463e-9699-334c9543e076";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext514_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext514__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext514__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext514__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext514__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext514__load_store_cache_byte_read_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext514_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE6",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE6",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext514__slm_byte_read_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext514_SLM_BYTE_READ_BANK0_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext515_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext515_SLM_BYTE_READ_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext515_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext515";
    metric_set->symbol_name = "Ext515";
    metric_set->hw_config_guid = "5a8af975-8ceb-4111-b13a-3584b5485afb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext515_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext515__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext515__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext515__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext515__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext515__load_store_cache_byte_read_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext515_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE7",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE7",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext515__slm_byte_read_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext515_SLM_BYTE_READ_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext516_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext516_SLM_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext516_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext516";
    metric_set->symbol_name = "Ext516";
    metric_set->hw_config_guid = "a0bd2654-8654-4aec-b9c3-609b7cfc7c29";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext516_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext516__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext516__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext516__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext516__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext516__load_store_cache_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext516_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext516__slm_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext516_SLM_BYTE_READ_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext517_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext517_SLM_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext517_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext517";
    metric_set->symbol_name = "Ext517";
    metric_set->hw_config_guid = "56c67cc8-4bbb-44bc-8552-1d095f1800bc";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext517_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext517__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext517__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext517__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext517__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext517__load_store_cache_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext517_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext517__slm_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext517_SLM_BYTE_READ_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext518_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext518_SLM_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext518_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext518";
    metric_set->symbol_name = "Ext518";
    metric_set->hw_config_guid = "f4f45c2b-4810-43db-a47d-cb854884f724";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext518_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext518__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext518__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext518__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext518__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext518__load_store_cache_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext518_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext518__slm_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext518_SLM_BYTE_READ_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext519_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext519_SLM_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext519_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext519";
    metric_set->symbol_name = "Ext519";
    metric_set->hw_config_guid = "58283b64-3a38-4985-b19c-db349947311a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext519_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext519__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext519__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext519__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext519__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext519__load_store_cache_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext519_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext519__slm_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext519_SLM_BYTE_READ_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext520_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext520_SLM_BYTE_READ_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext520_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext520";
    metric_set->symbol_name = "Ext520";
    metric_set->hw_config_guid = "144cc1f2-ff34-4ce7-8bb9-7cb6cee76403";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext520_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext520__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext520__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext520__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext520__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext520__load_store_cache_byte_read_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext520_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE4",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE4",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext520__slm_byte_read_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext520_SLM_BYTE_READ_BANK1_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext521_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext521_SLM_BYTE_READ_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext521_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext521";
    metric_set->symbol_name = "Ext521";
    metric_set->hw_config_guid = "9b5b6101-2131-4069-ace5-bcb3300991cb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext521_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext521__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext521__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext521__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext521__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext521__load_store_cache_byte_read_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext521_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE5",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE5",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext521__slm_byte_read_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext521_SLM_BYTE_READ_BANK1_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext522_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext522_SLM_BYTE_READ_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext522_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext522";
    metric_set->symbol_name = "Ext522";
    metric_set->hw_config_guid = "b3cfc81d-5297-483d-8e45-b77e4935fbe9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext522_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext522__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext522__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext522__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext522__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext522__load_store_cache_byte_read_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext522_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE6",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE6",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext522__slm_byte_read_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext522_SLM_BYTE_READ_BANK1_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext523_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext523_SLM_BYTE_READ_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext523_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext523";
    metric_set->symbol_name = "Ext523";
    metric_set->hw_config_guid = "1975278e-2c3f-49a3-891a-fc2ed8f22eec";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext523_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext523__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext523__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext523__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext523__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext523__load_store_cache_byte_read_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext523_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE7",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE7",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext523__slm_byte_read_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext523_SLM_BYTE_READ_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext524_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext524_SLM_BYTE_READ_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext524_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext524";
    metric_set->symbol_name = "Ext524";
    metric_set->hw_config_guid = "06d3fa26-617a-4443-a552-17937fc2bc83";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext524_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext524__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext524__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext524__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext524__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext524__load_store_cache_byte_read_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext524_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext524__slm_byte_read_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext524_SLM_BYTE_READ_BANK2_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext525_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext525_SLM_BYTE_READ_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext525_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext525";
    metric_set->symbol_name = "Ext525";
    metric_set->hw_config_guid = "5115960e-f55c-4854-bac4-b771c4185270";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext525_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext525__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext525__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext525__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext525__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext525__load_store_cache_byte_read_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext525_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext525__slm_byte_read_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext525_SLM_BYTE_READ_BANK2_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext526_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext526_SLM_BYTE_READ_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext526_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext526";
    metric_set->symbol_name = "Ext526";
    metric_set->hw_config_guid = "4dc30759-6119-4bf0-85b7-4a7cd5e79956";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext526_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext526__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext526__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext526__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext526__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext526__load_store_cache_byte_read_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext526_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext526__slm_byte_read_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext526_SLM_BYTE_READ_BANK2_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext527_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext527_SLM_BYTE_READ_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext527_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext527";
    metric_set->symbol_name = "Ext527";
    metric_set->hw_config_guid = "2060bec5-9739-4970-ab77-09dd7c107044";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext527_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext527__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext527__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext527__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext527__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext527__load_store_cache_byte_read_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext527_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext527__slm_byte_read_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext527_SLM_BYTE_READ_BANK2_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext528_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext528_SLM_BYTE_READ_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext528_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext528";
    metric_set->symbol_name = "Ext528";
    metric_set->hw_config_guid = "91384c6e-5087-43d6-a32f-699690ca8917";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext528_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext528__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext528__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext528__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext528__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE4",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext528__load_store_cache_byte_read_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext528_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE4_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE4",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE4",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext528__slm_byte_read_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext528_SLM_BYTE_READ_BANK2_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext529_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext529_SLM_BYTE_READ_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext529_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext529";
    metric_set->symbol_name = "Ext529";
    metric_set->hw_config_guid = "cb4f7554-9a12-4f83-a7c6-0ff8911f9e73";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext529_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext529__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext529__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext529__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext529__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE5",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext529__load_store_cache_byte_read_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext529_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE5_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE5",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE5",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext529__slm_byte_read_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext529_SLM_BYTE_READ_BANK2_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext530_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext530_SLM_BYTE_READ_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext530_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext530";
    metric_set->symbol_name = "Ext530";
    metric_set->hw_config_guid = "80502c88-9c1e-4804-8d54-53b3d784a540";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext530_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext530__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext530__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext530__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext530__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE6",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext530__load_store_cache_byte_read_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext530_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE6_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE6",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE6",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext530__slm_byte_read_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext530_SLM_BYTE_READ_BANK2_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext531_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext531_SLM_BYTE_READ_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext531_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext531";
    metric_set->symbol_name = "Ext531";
    metric_set->hw_config_guid = "eccbb94d-f7ed-4d45-89bb-d17a0e28e97d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext531_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext531__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext531__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext531__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext531__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK2 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE7",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext531__load_store_cache_byte_read_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext531_LOAD_STORE_CACHE_BYTE_READ_BANK2_XECORE7_availability,
            },

            {
                .name = "SLM BYTE READ BANK2 XECORE7",
                .symbol_name = "SLM_BYTE_READ_BANK2_XECORE7",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext531__slm_byte_read_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext531_SLM_BYTE_READ_BANK2_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext532_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext532_SLM_BYTE_READ_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext532_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext532";
    metric_set->symbol_name = "Ext532";
    metric_set->hw_config_guid = "09cb4790-899a-456f-9c12-f0b5ae36bf39";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext532_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext532__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext532__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext532__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext532__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext532__load_store_cache_byte_read_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext532_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext532__slm_byte_read_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext532_SLM_BYTE_READ_BANK3_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext533_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext533_SLM_BYTE_READ_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext533_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext533";
    metric_set->symbol_name = "Ext533";
    metric_set->hw_config_guid = "e257595b-2e38-4da5-b375-bc494b4d0ee8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext533_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext533__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext533__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext533__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext533__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext533__load_store_cache_byte_read_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext533_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE1_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext533__slm_byte_read_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext533_SLM_BYTE_READ_BANK3_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext534_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext534_SLM_BYTE_READ_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext534_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext534";
    metric_set->symbol_name = "Ext534";
    metric_set->hw_config_guid = "f2477c56-db39-43cf-bd4c-42782dd02e27";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext534_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext534__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext534__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext534__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext534__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext534__load_store_cache_byte_read_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext534_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext534__slm_byte_read_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext534_SLM_BYTE_READ_BANK3_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext535_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext535_SLM_BYTE_READ_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext535_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext535";
    metric_set->symbol_name = "Ext535";
    metric_set->hw_config_guid = "b6417928-9c95-4df7-88a2-e6b8de52abec";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext535_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext535__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext535__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext535__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext535__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext535__load_store_cache_byte_read_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext535_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE3_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext535__slm_byte_read_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext535_SLM_BYTE_READ_BANK3_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext536_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext536_SLM_BYTE_READ_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext536_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext536";
    metric_set->symbol_name = "Ext536";
    metric_set->hw_config_guid = "ac88f2a7-2f38-4e61-a6d5-9da2d50edd38";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext536_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext536__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext536__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext536__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext536__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE4",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext536__load_store_cache_byte_read_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext536_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE4_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE4",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE4",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext536__slm_byte_read_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext536_SLM_BYTE_READ_BANK3_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext537_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext537_SLM_BYTE_READ_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext537_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext537";
    metric_set->symbol_name = "Ext537";
    metric_set->hw_config_guid = "87640cd9-04b0-4b76-a016-308ab7975f8d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext537_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext537__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext537__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext537__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext537__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE5",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext537__load_store_cache_byte_read_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext537_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE5_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE5",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE5",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext537__slm_byte_read_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext537_SLM_BYTE_READ_BANK3_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext538_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext538_SLM_BYTE_READ_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext538_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext538";
    metric_set->symbol_name = "Ext538";
    metric_set->hw_config_guid = "2a2f8a81-b046-4a67-92c3-2ded36755f76";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext538_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext538__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext538__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext538__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext538__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE6",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext538__load_store_cache_byte_read_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext538_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE6_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE6",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE6",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext538__slm_byte_read_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext538_SLM_BYTE_READ_BANK3_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext539_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext539_SLM_BYTE_READ_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext539_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext539";
    metric_set->symbol_name = "Ext539";
    metric_set->hw_config_guid = "89f03450-0e5f-4370-b7cf-cea4e627d4e8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext539_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext539__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext539__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext539__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext539__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK3 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE7",
                .desc = "Number of bytes read out of the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext539__load_store_cache_byte_read_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext539_LOAD_STORE_CACHE_BYTE_READ_BANK3_XECORE7_availability,
            },

            {
                .name = "SLM BYTE READ BANK3 XECORE7",
                .symbol_name = "SLM_BYTE_READ_BANK3_XECORE7",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext539__slm_byte_read_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext539_SLM_BYTE_READ_BANK3_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext540_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext540_SLM_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext540_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext540";
    metric_set->symbol_name = "Ext540";
    metric_set->hw_config_guid = "85c7638d-976e-47e5-8f52-2079a0ea147f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext540_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext540__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext540__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext540__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext540__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext540__load_store_cache_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext540_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext540__slm_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext540_SLM_BYTE_WRITE_BANK0_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext541_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext541_SLM_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext541_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext541";
    metric_set->symbol_name = "Ext541";
    metric_set->hw_config_guid = "69645853-2e7f-4a77-83fc-fa03f43b5d35";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext541_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext541__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext541__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext541__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext541__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext541__load_store_cache_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext541_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext541__slm_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext541_SLM_BYTE_WRITE_BANK0_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext542_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext542_SLM_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext542_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext542";
    metric_set->symbol_name = "Ext542";
    metric_set->hw_config_guid = "657218aa-a73a-4127-b081-07ece46ff786";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext542_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext542__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext542__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext542__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext542__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext542__load_store_cache_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext542_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext542__slm_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext542_SLM_BYTE_WRITE_BANK0_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext543_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext543_SLM_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext543_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext543";
    metric_set->symbol_name = "Ext543";
    metric_set->hw_config_guid = "1a51853a-37a2-4020-8ccb-650604ea4f64";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext543_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext543__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext543__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext543__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext543__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext543__load_store_cache_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext543_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext543__slm_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext543_SLM_BYTE_WRITE_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext544_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext544_SLM_BYTE_WRITE_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext544_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext544";
    metric_set->symbol_name = "Ext544";
    metric_set->hw_config_guid = "9aa2e068-b13a-44b2-be93-a4cf68924cdd";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext544_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext544__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext544__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext544__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext544__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext544__load_store_cache_byte_write_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext544_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE4",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE4",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext544__slm_byte_write_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext544_SLM_BYTE_WRITE_BANK0_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext545_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext545_SLM_BYTE_WRITE_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext545_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext545";
    metric_set->symbol_name = "Ext545";
    metric_set->hw_config_guid = "5e8c65a2-97ac-4dea-af1b-27b9f12dafe6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext545_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext545__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext545__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext545__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext545__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext545__load_store_cache_byte_write_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext545_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE5",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE5",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext545__slm_byte_write_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext545_SLM_BYTE_WRITE_BANK0_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext546_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext546_SLM_BYTE_WRITE_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext546_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext546";
    metric_set->symbol_name = "Ext546";
    metric_set->hw_config_guid = "192ec14b-c329-4e81-bd2d-02f7cae24579";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext546_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext546__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext546__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext546__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext546__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext546__load_store_cache_byte_write_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext546_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE6",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE6",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext546__slm_byte_write_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext546_SLM_BYTE_WRITE_BANK0_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext547_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext547_SLM_BYTE_WRITE_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext547_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext547";
    metric_set->symbol_name = "Ext547";
    metric_set->hw_config_guid = "2e5ac978-b4e4-4693-8f88-d90d0353dd77";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext547_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext547__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext547__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext547__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext547__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext547__load_store_cache_byte_write_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext547_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE7",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE7",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext547__slm_byte_write_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext547_SLM_BYTE_WRITE_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext548_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext548_SLM_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext548_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext548";
    metric_set->symbol_name = "Ext548";
    metric_set->hw_config_guid = "7c95ba0f-cd85-4eb2-ab43-987f84214820";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext548_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext548__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext548__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext548__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext548__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext548__load_store_cache_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext548_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext548__slm_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext548_SLM_BYTE_WRITE_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext549_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext549_SLM_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext549_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext549";
    metric_set->symbol_name = "Ext549";
    metric_set->hw_config_guid = "8fa03693-d2d5-42eb-a382-e2cf05bf8197";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext549_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext549__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext549__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext549__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext549__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext549__load_store_cache_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext549_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext549__slm_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext549_SLM_BYTE_WRITE_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext550_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext550_SLM_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext550_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext550";
    metric_set->symbol_name = "Ext550";
    metric_set->hw_config_guid = "3714122b-03ee-499b-bc5f-31ed5400924e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext550_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext550__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext550__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext550__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext550__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext550__load_store_cache_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext550_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext550__slm_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext550_SLM_BYTE_WRITE_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext551_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext551_SLM_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext551_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext551";
    metric_set->symbol_name = "Ext551";
    metric_set->hw_config_guid = "31ed9c46-b219-4bcc-8c20-22586fb077f8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext551_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext551__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext551__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext551__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext551__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext551__load_store_cache_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext551_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext551__slm_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext551_SLM_BYTE_WRITE_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext552_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext552_SLM_BYTE_WRITE_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext552_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext552";
    metric_set->symbol_name = "Ext552";
    metric_set->hw_config_guid = "f639c566-949f-4484-8c12-5127fb771b4c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext552_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext552__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext552__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext552__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext552__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext552__load_store_cache_byte_write_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext552_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE4",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE4",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext552__slm_byte_write_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext552_SLM_BYTE_WRITE_BANK1_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext553_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext553_SLM_BYTE_WRITE_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext553_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext553";
    metric_set->symbol_name = "Ext553";
    metric_set->hw_config_guid = "40b20c9d-0935-4000-91d7-f312a515bb4b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext553_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext553__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext553__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext553__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext553__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext553__load_store_cache_byte_write_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext553_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE5",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE5",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext553__slm_byte_write_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext553_SLM_BYTE_WRITE_BANK1_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext554_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext554_SLM_BYTE_WRITE_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext554_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext554";
    metric_set->symbol_name = "Ext554";
    metric_set->hw_config_guid = "bcff8729-44e4-4efa-8436-f1775fcb204a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext554_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext554__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext554__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext554__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext554__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext554__load_store_cache_byte_write_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext554_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE6",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE6",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext554__slm_byte_write_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext554_SLM_BYTE_WRITE_BANK1_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext555_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext555_SLM_BYTE_WRITE_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext555_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext555";
    metric_set->symbol_name = "Ext555";
    metric_set->hw_config_guid = "6bf30c0e-a169-4ba3-8527-047d4f691aa3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext555_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext555__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext555__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext555__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext555__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext555__load_store_cache_byte_write_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext555_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE7",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE7",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext555__slm_byte_write_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext555_SLM_BYTE_WRITE_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext556_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext556_SLM_BYTE_WRITE_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext556_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext556";
    metric_set->symbol_name = "Ext556";
    metric_set->hw_config_guid = "bc1cda24-8e1b-4000-9443-1135be1b976e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext556_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext556__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext556__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext556__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext556__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext556__load_store_cache_byte_write_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext556_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext556__slm_byte_write_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext556_SLM_BYTE_WRITE_BANK2_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext557_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext557_SLM_BYTE_WRITE_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext557_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext557";
    metric_set->symbol_name = "Ext557";
    metric_set->hw_config_guid = "c8a172f8-4a06-4931-b877-bc8aa687a9b8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext557_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext557__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext557__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext557__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext557__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext557__load_store_cache_byte_write_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext557_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext557__slm_byte_write_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext557_SLM_BYTE_WRITE_BANK2_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext558_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext558_SLM_BYTE_WRITE_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext558_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext558";
    metric_set->symbol_name = "Ext558";
    metric_set->hw_config_guid = "a5a9b5ed-c78c-4e3d-a808-22f1debd6b43";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext558_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext558__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext558__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext558__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext558__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext558__load_store_cache_byte_write_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext558_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext558__slm_byte_write_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext558_SLM_BYTE_WRITE_BANK2_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext559_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext559_SLM_BYTE_WRITE_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext559_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext559";
    metric_set->symbol_name = "Ext559";
    metric_set->hw_config_guid = "93bba39f-4d65-434b-9251-37f2badf256e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext559_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext559__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext559__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext559__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext559__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext559__load_store_cache_byte_write_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext559_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext559__slm_byte_write_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext559_SLM_BYTE_WRITE_BANK2_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext560_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext560_SLM_BYTE_WRITE_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext560_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext560";
    metric_set->symbol_name = "Ext560";
    metric_set->hw_config_guid = "a16d5961-ab03-4193-87d9-394ad9c2da80";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext560_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext560__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext560__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext560__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext560__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE4",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext560__load_store_cache_byte_write_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext560_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE4_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE4",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE4",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext560__slm_byte_write_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext560_SLM_BYTE_WRITE_BANK2_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext561_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext561_SLM_BYTE_WRITE_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext561_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext561";
    metric_set->symbol_name = "Ext561";
    metric_set->hw_config_guid = "8dfd3f4a-0686-48bb-94cf-76a3bc5386ec";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext561_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext561__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext561__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext561__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext561__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE5",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext561__load_store_cache_byte_write_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext561_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE5_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE5",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE5",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext561__slm_byte_write_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext561_SLM_BYTE_WRITE_BANK2_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext562_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext562_SLM_BYTE_WRITE_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext562_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext562";
    metric_set->symbol_name = "Ext562";
    metric_set->hw_config_guid = "f41e3a7c-de83-46af-8be2-b26c605d1317";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext562_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext562__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext562__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext562__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext562__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE6",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext562__load_store_cache_byte_write_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext562_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE6_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE6",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE6",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext562__slm_byte_write_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext562_SLM_BYTE_WRITE_BANK2_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext563_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext563_SLM_BYTE_WRITE_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext563_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext563";
    metric_set->symbol_name = "Ext563";
    metric_set->hw_config_guid = "c599736d-1b09-4ae6-9e82-c98d17c3582a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext563_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext563__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext563__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext563__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext563__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK2 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE7",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext563__load_store_cache_byte_write_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext563_LOAD_STORE_CACHE_BYTE_WRITE_BANK2_XECORE7_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK2 XECORE7",
                .symbol_name = "SLM_BYTE_WRITE_BANK2_XECORE7",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext563__slm_byte_write_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext563_SLM_BYTE_WRITE_BANK2_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext564_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext564_SLM_BYTE_WRITE_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext564_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext564";
    metric_set->symbol_name = "Ext564";
    metric_set->hw_config_guid = "0f9c5fb0-e5bc-4119-a11f-d32d0304bca8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext564_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext564__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext564__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext564__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext564__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext564__load_store_cache_byte_write_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext564_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext564__slm_byte_write_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext564_SLM_BYTE_WRITE_BANK3_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext565_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext565_SLM_BYTE_WRITE_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext565_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext565";
    metric_set->symbol_name = "Ext565";
    metric_set->hw_config_guid = "def2b365-d8d1-4e4b-b832-39afd5e214d9";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext565_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext565__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext565__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext565__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext565__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext565__load_store_cache_byte_write_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext565_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext565__slm_byte_write_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext565_SLM_BYTE_WRITE_BANK3_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext566_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext566_SLM_BYTE_WRITE_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext566_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext566";
    metric_set->symbol_name = "Ext566";
    metric_set->hw_config_guid = "a53e91c2-03b4-488a-ab7e-293f4466e00f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext566_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext566__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext566__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext566__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext566__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext566__load_store_cache_byte_write_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext566_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext566__slm_byte_write_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext566_SLM_BYTE_WRITE_BANK3_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext567_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext567_SLM_BYTE_WRITE_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 2, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext567_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext567";
    metric_set->symbol_name = "Ext567";
    metric_set->hw_config_guid = "0cdefa4f-f4ac-4072-a021-be48ed5b0ee7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext567_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext567__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext567__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext567__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext567__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext567__load_store_cache_byte_write_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext567_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext567__slm_byte_write_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext567_SLM_BYTE_WRITE_BANK3_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext568_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext568_SLM_BYTE_WRITE_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 0)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext568_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext568";
    metric_set->symbol_name = "Ext568";
    metric_set->hw_config_guid = "7404a462-f9c0-4fb6-9ec9-b03bbd5e4572";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext568_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext568__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext568__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext568__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext568__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE4",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext568__load_store_cache_byte_write_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext568_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE4_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE4",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE4",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext568__slm_byte_write_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext568_SLM_BYTE_WRITE_BANK3_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext569_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext569_SLM_BYTE_WRITE_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 1)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext569_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext569";
    metric_set->symbol_name = "Ext569";
    metric_set->hw_config_guid = "b3515130-788c-4d36-b20d-e8ca02e11cf1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext569_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext569__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext569__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext569__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext569__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE5",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext569__load_store_cache_byte_write_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext569_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE5_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE5",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE5",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext569__slm_byte_write_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext569_SLM_BYTE_WRITE_BANK3_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext570_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext570_SLM_BYTE_WRITE_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 2)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext570_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext570";
    metric_set->symbol_name = "Ext570";
    metric_set->hw_config_guid = "73e5a9f9-ca88-4467-b407-737e7c7080fe";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext570_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext570__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext570__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext570__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext570__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE6",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext570__load_store_cache_byte_write_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext570_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE6_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE6",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE6",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext570__slm_byte_write_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext570_SLM_BYTE_WRITE_BANK3_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool acmgt1_ext571_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}
static bool acmgt1_ext571_SLM_BYTE_WRITE_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 3, 3)) {
        return true;
    }
    return false;
}

static void
acmgt1_add_ext571_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext571";
    metric_set->symbol_name = "Ext571";
    metric_set->hw_config_guid = "ae2fa4f6-2afb-4ac9-866e-bfd943f91a54";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext571_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext571__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext571__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext571__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext571__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK3 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE7",
                .desc = "Number of bytes written to the Load Store Cache, excluding SLM accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext571__load_store_cache_byte_write_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext571_LOAD_STORE_CACHE_BYTE_WRITE_BANK3_XECORE7_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK3 XECORE7",
                .symbol_name = "SLM_BYTE_WRITE_BANK3_XECORE7",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = acmgt1__ext571__slm_byte_write_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L1Cache",
                .availability = acmgt1_ext571_SLM_BYTE_WRITE_BANK3_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}


static void
acmgt1_add_ext1000_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1000";
    metric_set->symbol_name = "Ext1000";
    metric_set->hw_config_guid = "cea714fc-17a9-4dae-b3e8-8be0f3149918";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1000_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1000__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1000__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1000__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1000__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE ACTIVE CYCLES",
                .symbol_name = "XVE_ACTIVE_CYCLES",
                .desc = "Number of cycles at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_active_cycles__read,
                .max_uint64 = acmgt1__ext1000__xve_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt1__ext1000__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt1__ext1000__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL",
                .desc = "Number of instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_inst_executed_control_all__read,
                .max_uint64 = acmgt1__ext1000__xve_inst_executed_control_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_inst_executed_control_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt1__ext1000__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt1__ext1000__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE",
                .desc = "Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_pipe_alu0_and_alu1_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE_CYCLES",
                .desc = "Number of cycles in ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read,
                .max_uint64 = acmgt1__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE",
                .desc = "Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_pipe_alu0_and_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE_CYCLES",
                .desc = "Number of cycles ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read,
                .max_uint64 = acmgt1__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_stall_cycles__read,
                .max_uint64 = acmgt1__ext1000__xve_stall_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1000__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE THREADS OCCUPANCY CYCLES ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_CYCLES_ALL",
                .desc = "Number of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1000__xve_threads_occupancy_cycles_all__read,
                .max_uint64 = acmgt1__ext1000__xve_threads_occupancy_cycles_all__max,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt1_add_ext1001_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1001";
    metric_set->symbol_name = "Ext1001";
    metric_set->hw_config_guid = "3ec074a8-e3cb-4090-86c0-0d1426ac9a63";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1001_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1001__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1001__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1001__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1001__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_async_cs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu0_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_cs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu0_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_ds__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu0_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_hs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu0_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_ps__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu0_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_vs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu0_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu0_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_async_cs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu1_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_cs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu1_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_ds__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu1_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_hs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu1_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_ps__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu1_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_vs__read,
                .max_uint64 = acmgt1__ext1001__xve_inst_executed_alu1_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1001__xve_inst_executed_alu1_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt1_add_ext1002_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1002";
    metric_set->symbol_name = "Ext1002";
    metric_set->hw_config_guid = "17275fa7-be46-48a6-a654-6931ecbfed77";
    metric_set->counters = calloc(21, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1002_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1002__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1002__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1002__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1002__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_alu0_rt_chs__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_alu0_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_alu0_rt_ms__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_alu0_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_alu1_rt_chs__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_alu1_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_alu1_rt_ms__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_alu1_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS",
                .desc = "Number of instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_send_rt_ahs__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_send_rt_ahs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_send_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS",
                .desc = "Number of instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_send_rt_chs__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_send_rt_chs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_send_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS",
                .desc = "Number of instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1002__xve_inst_executed_send_rt_ms__read,
                .max_uint64 = acmgt1__ext1002__xve_inst_executed_send_rt_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1002__xve_inst_executed_send_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 21);
}


static void
acmgt1_add_ext1004_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1004";
    metric_set->symbol_name = "Ext1004";
    metric_set->hw_config_guid = "a56f028c-27c7-4e9b-bc19-04bbf67444b0";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1004_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1004__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1004__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1004__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1004__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL ASYNC CS",
                .symbol_name = "XVE_STALL_ASYNC_CS",
                .desc = "Percentage of time in which there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_async_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CS",
                .symbol_name = "XVE_STALL_CS",
                .desc = "Percentage of time in which there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES ASYNC CS",
                .symbol_name = "XVE_STALL_CYCLES_ASYNC_CS",
                .desc = "Number of cycles there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_async_cs__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES CS",
                .symbol_name = "XVE_STALL_CYCLES_CS",
                .desc = "Number of cycles there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_cs__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES DS",
                .symbol_name = "XVE_STALL_CYCLES_DS",
                .desc = "Number of cycles there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_ds__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES HS",
                .symbol_name = "XVE_STALL_CYCLES_HS",
                .desc = "Number of cycles there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_hs__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES MS",
                .symbol_name = "XVE_STALL_CYCLES_MS",
                .desc = "Number of cycles there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_ms__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES FS",
                .symbol_name = "XVE_STALL_CYCLES_PS",
                .desc = "Number of cycles there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_ps__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES RT",
                .symbol_name = "XVE_STALL_CYCLES_RT",
                .desc = "Number of cycles there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_rt__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_rt__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES TS",
                .symbol_name = "XVE_STALL_CYCLES_TS",
                .desc = "Number of cycles there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_ts__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES VS",
                .symbol_name = "XVE_STALL_CYCLES_VS",
                .desc = "Number of cycles there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1004__xve_stall_cycles_vs__read,
                .max_uint64 = acmgt1__ext1004__xve_stall_cycles_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL DS",
                .symbol_name = "XVE_STALL_DS",
                .desc = "Percentage of time in which there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_ds__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL HS",
                .symbol_name = "XVE_STALL_HS",
                .desc = "Percentage of time in which there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_hs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL MS",
                .symbol_name = "XVE_STALL_MS",
                .desc = "Percentage of time in which there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_ms__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL FS",
                .symbol_name = "XVE_STALL_PS",
                .desc = "Percentage of time in which there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_ps__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL RT",
                .symbol_name = "XVE_STALL_RT",
                .desc = "Percentage of time in which there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_rt__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL TS",
                .symbol_name = "XVE_STALL_TS",
                .desc = "Percentage of time in which there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_ts__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL VS",
                .symbol_name = "XVE_STALL_VS",
                .desc = "Percentage of time in which there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1004__xve_stall_vs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt1_add_ext1005_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1005";
    metric_set->symbol_name = "Ext1005";
    metric_set->hw_config_guid = "f43c884f-817d-4037-bc96-7bed64906683";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1005_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1005__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1005__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1005__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1005__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_alu0_all__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_alu0_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_alu1_all__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_alu1_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP16",
                .symbol_name = "XVE_INST_EXECUTED_FP16",
                .desc = "Number of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_fp16__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_fp16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP32",
                .symbol_name = "XVE_INST_EXECUTED_FP32",
                .desc = "Number of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_fp32__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_fp32__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP32_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_fp32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP64",
                .symbol_name = "XVE_INST_EXECUTED_FP64",
                .desc = "The number of FLT64 instructions executed in ALU0 INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_fp64__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_fp64__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED FP64 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP64_UTILIZATION",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_fp64_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT16",
                .symbol_name = "XVE_INST_EXECUTED_INT16",
                .desc = "Number of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_int16__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_int16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT16_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_int16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT32",
                .symbol_name = "XVE_INST_EXECUTED_INT32",
                .desc = "Number of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_int32__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_int32__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED INT32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT32_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_int32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED MATH",
                .symbol_name = "XVE_INST_EXECUTED_MATH",
                .desc = "Number of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_math__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_math__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED MATH UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_MATH_UTILIZATION",
                .desc = "Percentage of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_math_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_all__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16",
                .desc = "Number of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_bf16__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_bf16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16_UTILIZATION",
                .desc = "Percentage of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_xmx_bf16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16",
                .desc = "Number of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_fp16__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_fp16__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_xmx_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8",
                .desc = "Number of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_int8__read,
                .max_uint64 = acmgt1__ext1005__xve_inst_executed_xmx_int8__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1005__xve_inst_executed_xmx_int8_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
acmgt1_add_ext1006_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1006";
    metric_set->symbol_name = "Ext1006";
    metric_set->hw_config_guid = "6a6e8e1d-6148-4316-95f9-2a8b5236520f";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1006_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1006__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1006__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1006__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1006__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_all__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_all__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS",
                .desc = "Number of instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_async_cs__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_async_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS",
                .desc = "Number of instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_cs__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_cs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND DS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS",
                .desc = "Number of instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_ds__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_ds__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND GS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS",
                .desc = "Number of instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_gs__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND HS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS",
                .desc = "Number of instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_hs__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_hs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS",
                .desc = "Number of instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_ms__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND FS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS",
                .desc = "Number of instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_ps__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_ps__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND TS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS",
                .desc = "Number of instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_ts__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND VS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS",
                .desc = "Number of instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1006__xve_inst_executed_send_vs__read,
                .max_uint64 = acmgt1__ext1006__xve_inst_executed_send_vs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED SEND VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1006__xve_inst_executed_send_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
acmgt1_add_ext1007_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1007";
    metric_set->symbol_name = "Ext1007";
    metric_set->hw_config_guid = "b6b53888-0a0b-4fc6-b77e-c604875495a5";
    metric_set->counters = calloc(17, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1007_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1007__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1007__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1007__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1007__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1007__xve_inst_executed_alu0_gs__read,
                .max_uint64 = acmgt1__ext1007__xve_inst_executed_alu0_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1007__xve_inst_executed_alu0_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1007__xve_inst_executed_alu0_ms__read,
                .max_uint64 = acmgt1__ext1007__xve_inst_executed_alu0_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1007__xve_inst_executed_alu0_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1007__xve_inst_executed_alu0_ts__read,
                .max_uint64 = acmgt1__ext1007__xve_inst_executed_alu0_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1007__xve_inst_executed_alu0_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1007__xve_inst_executed_alu1_gs__read,
                .max_uint64 = acmgt1__ext1007__xve_inst_executed_alu1_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1007__xve_inst_executed_alu1_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1007__xve_inst_executed_alu1_ms__read,
                .max_uint64 = acmgt1__ext1007__xve_inst_executed_alu1_ms__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1007__xve_inst_executed_alu1_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1007__xve_inst_executed_alu1_ts__read,
                .max_uint64 = acmgt1__ext1007__xve_inst_executed_alu1_ts__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1007__xve_inst_executed_alu1_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL CYCLES GS",
                .symbol_name = "XVE_STALL_CYCLES_GS",
                .desc = "Number of cycles there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = acmgt1__ext1007__xve_stall_cycles_gs__read,
                .max_uint64 = acmgt1__ext1007__xve_stall_cycles_gs__max,
                .group = "VectorEngine",
            },

            {
                .name = "XVE STALL GS",
                .symbol_name = "XVE_STALL_GS",
                .desc = "Percentage of time in which there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = acmgt1__ext1007__xve_stall_gs__read,
                .max_float = percentage_max_callback_float,
                .group = "VectorEngine",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 17);
}


static void
acmgt1_add_ext1010_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1010";
    metric_set->symbol_name = "Ext1010";
    metric_set->hw_config_guid = "6e06382a-3c98-464a-9811-cdfb956e4e8e";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    acmgt1_ext1010_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = acmgt1__ext1010__avg_gpu_core_frequency__read,
                .max_uint64 = acmgt1__ext1010__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = acmgt1__ext1010__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = acmgt1__ext1010__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL BLEND",
                .symbol_name = "PIXEL_BLEND",
                .desc = "Number of blended 2x2 pixels written to all render targets",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt1__ext1010__pixel_blend__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "PIXEL WRITE",
                .symbol_name = "PIXEL_WRITE",
                .desc = "Number of 2x2 pixels written to all render targets",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt1__ext1010__pixel_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "POSTPS DEPTH STENCIL ALPHA TEST FAIL",
                .symbol_name = "POSTPS_DEPTH_STENCIL_ALPHA_TEST_FAIL",
                .desc = "Number of 2x2 that were lit from Rasterizer but failed the depth stencil test or alpha test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt1__ext1010__postps_depth_stencil_alpha_test_fail__read,
                .max_uint64 = NULL /* undefined */,
                .group = "ColorPipe",
            },

            {
                .name = "RASTERIZER SAMPLE OUTPUT",
                .symbol_name = "RASTERIZER_SAMPLE_OUTPUT",
                .desc = "Number of lit samples emitted by Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = acmgt1__ext1010__rasterizer_sample_output__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Rasterizer",
            },

            {
                .name = "SAMPLER 2X2 READ",
                .symbol_name = "SAMPLER_2X2_READ",
                .desc = "Number of 2x2 texel block requested from Sampler",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = acmgt1__ext1010__sampler_2_x2_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}

void
intel_perf_load_metrics_acmgt1(struct intel_perf *perf)
{
    acmgt1_add_render_basic_metric_set(perf);
    acmgt1_add_compute_basic_metric_set(perf);
    acmgt1_add_threads_and_rast1_metric_set(perf);
    acmgt1_add_threads_and_rast2_metric_set(perf);
    acmgt1_add_threads_and_rast3_metric_set(perf);
    acmgt1_add_threads_and_rast4_metric_set(perf);
    acmgt1_add_async_compute_metric_set(perf);
    acmgt1_add_xve_activity1_metric_set(perf);
    acmgt1_add_gpu_busyness_metric_set(perf);
    acmgt1_add_render_pipe_profile1_metric_set(perf);
    acmgt1_add_render_pipe_profile2_metric_set(perf);
    acmgt1_add_l3_metric_set(perf);
    acmgt1_add_sampler_metric_set(perf);
    acmgt1_add_hdc_and_sf1_metric_set(perf);
    acmgt1_add_hdc_and_sf2_metric_set(perf);
    acmgt1_add_rasterizer_and_pixel_backend1_metric_set(perf);
    acmgt1_add_rasterizer_and_pixel_backend2_metric_set(perf);
    acmgt1_add_tdl1_metric_set(perf);
    acmgt1_add_tdl2_metric_set(perf);
    acmgt1_add_tdl3_metric_set(perf);
    acmgt1_add_tdl4_metric_set(perf);
    acmgt1_add_test_oa_metric_set(perf);
    acmgt1_add_compute_overview_metric_set(perf);
    acmgt1_add_l1_profile_reads__xe_core0_metric_set(perf);
    acmgt1_add_l1_profile_reads__xe_core3_metric_set(perf);
    acmgt1_add_l1_profile_slm_bank_conflicts__xe_core0_metric_set(perf);
    acmgt1_add_l1_profile_slm_bank_conflicts__xe_core3_metric_set(perf);
    acmgt1_add_l1_profile_writes__xe_core0_metric_set(perf);
    acmgt1_add_l1_profile_writes__xe_core3_metric_set(perf);
    acmgt1_add_dataport_reads_metric_set(perf);
    acmgt1_add_dataport_writes_metric_set(perf);
    acmgt1_add_ext1_metric_set(perf);
    acmgt1_add_ext2_metric_set(perf);
    acmgt1_add_ext3_metric_set(perf);
    acmgt1_add_ext4_metric_set(perf);
    acmgt1_add_ext5_metric_set(perf);
    acmgt1_add_ext6_metric_set(perf);
    acmgt1_add_ext7_metric_set(perf);
    acmgt1_add_ext8_metric_set(perf);
    acmgt1_add_ext9_metric_set(perf);
    acmgt1_add_ext10_metric_set(perf);
    acmgt1_add_ext11_metric_set(perf);
    acmgt1_add_ext12_metric_set(perf);
    acmgt1_add_ext13_metric_set(perf);
    acmgt1_add_ext14_metric_set(perf);
    acmgt1_add_ext15_metric_set(perf);
    acmgt1_add_ext16_metric_set(perf);
    acmgt1_add_ext17_metric_set(perf);
    acmgt1_add_ext18_metric_set(perf);
    acmgt1_add_ext19_metric_set(perf);
    acmgt1_add_ext20_metric_set(perf);
    acmgt1_add_ext21_metric_set(perf);
    acmgt1_add_ext22_metric_set(perf);
    acmgt1_add_ext23_metric_set(perf);
    acmgt1_add_ext24_metric_set(perf);
    acmgt1_add_ext25_metric_set(perf);
    acmgt1_add_ext26_metric_set(perf);
    acmgt1_add_ext27_metric_set(perf);
    acmgt1_add_ext28_metric_set(perf);
    acmgt1_add_ext29_metric_set(perf);
    acmgt1_add_ext30_metric_set(perf);
    acmgt1_add_ext31_metric_set(perf);
    acmgt1_add_ext32_metric_set(perf);
    acmgt1_add_ext33_metric_set(perf);
    acmgt1_add_ext34_metric_set(perf);
    acmgt1_add_ext35_metric_set(perf);
    acmgt1_add_ext36_metric_set(perf);
    acmgt1_add_ext37_metric_set(perf);
    acmgt1_add_ext38_metric_set(perf);
    acmgt1_add_ext39_metric_set(perf);
    acmgt1_add_ext40_metric_set(perf);
    acmgt1_add_ext41_metric_set(perf);
    acmgt1_add_ext42_metric_set(perf);
    acmgt1_add_ext43_metric_set(perf);
    acmgt1_add_ext44_metric_set(perf);
    acmgt1_add_ext45_metric_set(perf);
    acmgt1_add_ext46_metric_set(perf);
    acmgt1_add_ext47_metric_set(perf);
    acmgt1_add_ext48_metric_set(perf);
    acmgt1_add_ext49_metric_set(perf);
    acmgt1_add_ext50_metric_set(perf);
    acmgt1_add_ext51_metric_set(perf);
    acmgt1_add_ext52_metric_set(perf);
    acmgt1_add_ext53_metric_set(perf);
    acmgt1_add_ext54_metric_set(perf);
    acmgt1_add_ext55_metric_set(perf);
    acmgt1_add_ext56_metric_set(perf);
    acmgt1_add_ext57_metric_set(perf);
    acmgt1_add_ext58_metric_set(perf);
    acmgt1_add_ext59_metric_set(perf);
    acmgt1_add_ext60_metric_set(perf);
    acmgt1_add_ext61_metric_set(perf);
    acmgt1_add_ext62_metric_set(perf);
    acmgt1_add_ext63_metric_set(perf);
    acmgt1_add_ext64_metric_set(perf);
    acmgt1_add_ext65_metric_set(perf);
    acmgt1_add_ext66_metric_set(perf);
    acmgt1_add_ext67_metric_set(perf);
    acmgt1_add_ext68_metric_set(perf);
    acmgt1_add_ext69_metric_set(perf);
    acmgt1_add_ext70_metric_set(perf);
    acmgt1_add_ext71_metric_set(perf);
    acmgt1_add_ext72_metric_set(perf);
    acmgt1_add_ext73_metric_set(perf);
    acmgt1_add_ext74_metric_set(perf);
    acmgt1_add_ext75_metric_set(perf);
    acmgt1_add_ext76_metric_set(perf);
    acmgt1_add_ext77_metric_set(perf);
    acmgt1_add_ext78_metric_set(perf);
    acmgt1_add_ext79_metric_set(perf);
    acmgt1_add_ext80_metric_set(perf);
    acmgt1_add_ext81_metric_set(perf);
    acmgt1_add_ext82_metric_set(perf);
    acmgt1_add_ext83_metric_set(perf);
    acmgt1_add_ext84_metric_set(perf);
    acmgt1_add_ext85_metric_set(perf);
    acmgt1_add_ext86_metric_set(perf);
    acmgt1_add_ext87_metric_set(perf);
    acmgt1_add_ext88_metric_set(perf);
    acmgt1_add_ext91_metric_set(perf);
    acmgt1_add_ext92_metric_set(perf);
    acmgt1_add_ext93_metric_set(perf);
    acmgt1_add_ext94_metric_set(perf);
    acmgt1_add_ext95_metric_set(perf);
    acmgt1_add_ext96_metric_set(perf);
    acmgt1_add_ext97_metric_set(perf);
    acmgt1_add_ext98_metric_set(perf);
    acmgt1_add_ext99_metric_set(perf);
    acmgt1_add_ext100_metric_set(perf);
    acmgt1_add_ext101_metric_set(perf);
    acmgt1_add_ext102_metric_set(perf);
    acmgt1_add_ext103_metric_set(perf);
    acmgt1_add_ext104_metric_set(perf);
    acmgt1_add_ext105_metric_set(perf);
    acmgt1_add_ext106_metric_set(perf);
    acmgt1_add_ext107_metric_set(perf);
    acmgt1_add_ext108_metric_set(perf);
    acmgt1_add_ext109_metric_set(perf);
    acmgt1_add_ext110_metric_set(perf);
    acmgt1_add_ext111_metric_set(perf);
    acmgt1_add_ext112_metric_set(perf);
    acmgt1_add_ext113_metric_set(perf);
    acmgt1_add_ext114_metric_set(perf);
    acmgt1_add_ext115_metric_set(perf);
    acmgt1_add_ext116_metric_set(perf);
    acmgt1_add_ext117_metric_set(perf);
    acmgt1_add_ext118_metric_set(perf);
    acmgt1_add_ext119_metric_set(perf);
    acmgt1_add_ext120_metric_set(perf);
    acmgt1_add_ext121_metric_set(perf);
    acmgt1_add_ext122_metric_set(perf);
    acmgt1_add_ext123_metric_set(perf);
    acmgt1_add_ext124_metric_set(perf);
    acmgt1_add_ext125_metric_set(perf);
    acmgt1_add_ext126_metric_set(perf);
    acmgt1_add_ext127_metric_set(perf);
    acmgt1_add_ext128_metric_set(perf);
    acmgt1_add_ext129_metric_set(perf);
    acmgt1_add_ext130_metric_set(perf);
    acmgt1_add_ext131_metric_set(perf);
    acmgt1_add_ext132_metric_set(perf);
    acmgt1_add_ext133_metric_set(perf);
    acmgt1_add_ext134_metric_set(perf);
    acmgt1_add_ext135_metric_set(perf);
    acmgt1_add_ext136_metric_set(perf);
    acmgt1_add_ext137_metric_set(perf);
    acmgt1_add_ext138_metric_set(perf);
    acmgt1_add_ext139_metric_set(perf);
    acmgt1_add_ext140_metric_set(perf);
    acmgt1_add_ext141_metric_set(perf);
    acmgt1_add_ext142_metric_set(perf);
    acmgt1_add_ext143_metric_set(perf);
    acmgt1_add_ext144_metric_set(perf);
    acmgt1_add_ext145_metric_set(perf);
    acmgt1_add_ext146_metric_set(perf);
    acmgt1_add_ext147_metric_set(perf);
    acmgt1_add_ext148_metric_set(perf);
    acmgt1_add_ext149_metric_set(perf);
    acmgt1_add_ext150_metric_set(perf);
    acmgt1_add_ext151_metric_set(perf);
    acmgt1_add_ext152_metric_set(perf);
    acmgt1_add_ext153_metric_set(perf);
    acmgt1_add_ext154_metric_set(perf);
    acmgt1_add_ext155_metric_set(perf);
    acmgt1_add_ext156_metric_set(perf);
    acmgt1_add_ext157_metric_set(perf);
    acmgt1_add_ext158_metric_set(perf);
    acmgt1_add_ext159_metric_set(perf);
    acmgt1_add_ext160_metric_set(perf);
    acmgt1_add_ext161_metric_set(perf);
    acmgt1_add_ext162_metric_set(perf);
    acmgt1_add_ext163_metric_set(perf);
    acmgt1_add_ext164_metric_set(perf);
    acmgt1_add_ext165_metric_set(perf);
    acmgt1_add_ext166_metric_set(perf);
    acmgt1_add_ext167_metric_set(perf);
    acmgt1_add_ext168_metric_set(perf);
    acmgt1_add_ext169_metric_set(perf);
    acmgt1_add_ext170_metric_set(perf);
    acmgt1_add_ext171_metric_set(perf);
    acmgt1_add_ext172_metric_set(perf);
    acmgt1_add_ext173_metric_set(perf);
    acmgt1_add_ext174_metric_set(perf);
    acmgt1_add_ext175_metric_set(perf);
    acmgt1_add_ext176_metric_set(perf);
    acmgt1_add_ext177_metric_set(perf);
    acmgt1_add_ext178_metric_set(perf);
    acmgt1_add_ext179_metric_set(perf);
    acmgt1_add_ext180_metric_set(perf);
    acmgt1_add_ext181_metric_set(perf);
    acmgt1_add_ext182_metric_set(perf);
    acmgt1_add_ext183_metric_set(perf);
    acmgt1_add_ext184_metric_set(perf);
    acmgt1_add_ext185_metric_set(perf);
    acmgt1_add_ext186_metric_set(perf);
    acmgt1_add_ext187_metric_set(perf);
    acmgt1_add_ext188_metric_set(perf);
    acmgt1_add_ext189_metric_set(perf);
    acmgt1_add_ext190_metric_set(perf);
    acmgt1_add_ext191_metric_set(perf);
    acmgt1_add_ext192_metric_set(perf);
    acmgt1_add_ext193_metric_set(perf);
    acmgt1_add_ext194_metric_set(perf);
    acmgt1_add_ext195_metric_set(perf);
    acmgt1_add_ext196_metric_set(perf);
    acmgt1_add_ext197_metric_set(perf);
    acmgt1_add_ext198_metric_set(perf);
    acmgt1_add_ext199_metric_set(perf);
    acmgt1_add_ext200_metric_set(perf);
    acmgt1_add_ext201_metric_set(perf);
    acmgt1_add_ext202_metric_set(perf);
    acmgt1_add_ext203_metric_set(perf);
    acmgt1_add_ext204_metric_set(perf);
    acmgt1_add_ext205_metric_set(perf);
    acmgt1_add_ext206_metric_set(perf);
    acmgt1_add_ext207_metric_set(perf);
    acmgt1_add_ext208_metric_set(perf);
    acmgt1_add_ext209_metric_set(perf);
    acmgt1_add_ext210_metric_set(perf);
    acmgt1_add_ext211_metric_set(perf);
    acmgt1_add_ext212_metric_set(perf);
    acmgt1_add_ext213_metric_set(perf);
    acmgt1_add_ext214_metric_set(perf);
    acmgt1_add_ext215_metric_set(perf);
    acmgt1_add_ext216_metric_set(perf);
    acmgt1_add_ext217_metric_set(perf);
    acmgt1_add_ext218_metric_set(perf);
    acmgt1_add_ext219_metric_set(perf);
    acmgt1_add_ext220_metric_set(perf);
    acmgt1_add_ext221_metric_set(perf);
    acmgt1_add_ext222_metric_set(perf);
    acmgt1_add_ext223_metric_set(perf);
    acmgt1_add_ext224_metric_set(perf);
    acmgt1_add_ext225_metric_set(perf);
    acmgt1_add_ext226_metric_set(perf);
    acmgt1_add_ext227_metric_set(perf);
    acmgt1_add_ext228_metric_set(perf);
    acmgt1_add_ext229_metric_set(perf);
    acmgt1_add_ext230_metric_set(perf);
    acmgt1_add_ext231_metric_set(perf);
    acmgt1_add_ext232_metric_set(perf);
    acmgt1_add_ext233_metric_set(perf);
    acmgt1_add_ext234_metric_set(perf);
    acmgt1_add_ext235_metric_set(perf);
    acmgt1_add_ext236_metric_set(perf);
    acmgt1_add_ext237_metric_set(perf);
    acmgt1_add_ext238_metric_set(perf);
    acmgt1_add_ext239_metric_set(perf);
    acmgt1_add_ext240_metric_set(perf);
    acmgt1_add_ext500_metric_set(perf);
    acmgt1_add_ext501_metric_set(perf);
    acmgt1_add_ext502_metric_set(perf);
    acmgt1_add_ext503_metric_set(perf);
    acmgt1_add_ext508_metric_set(perf);
    acmgt1_add_ext509_metric_set(perf);
    acmgt1_add_ext510_metric_set(perf);
    acmgt1_add_ext511_metric_set(perf);
    acmgt1_add_ext512_metric_set(perf);
    acmgt1_add_ext513_metric_set(perf);
    acmgt1_add_ext514_metric_set(perf);
    acmgt1_add_ext515_metric_set(perf);
    acmgt1_add_ext516_metric_set(perf);
    acmgt1_add_ext517_metric_set(perf);
    acmgt1_add_ext518_metric_set(perf);
    acmgt1_add_ext519_metric_set(perf);
    acmgt1_add_ext520_metric_set(perf);
    acmgt1_add_ext521_metric_set(perf);
    acmgt1_add_ext522_metric_set(perf);
    acmgt1_add_ext523_metric_set(perf);
    acmgt1_add_ext524_metric_set(perf);
    acmgt1_add_ext525_metric_set(perf);
    acmgt1_add_ext526_metric_set(perf);
    acmgt1_add_ext527_metric_set(perf);
    acmgt1_add_ext528_metric_set(perf);
    acmgt1_add_ext529_metric_set(perf);
    acmgt1_add_ext530_metric_set(perf);
    acmgt1_add_ext531_metric_set(perf);
    acmgt1_add_ext532_metric_set(perf);
    acmgt1_add_ext533_metric_set(perf);
    acmgt1_add_ext534_metric_set(perf);
    acmgt1_add_ext535_metric_set(perf);
    acmgt1_add_ext536_metric_set(perf);
    acmgt1_add_ext537_metric_set(perf);
    acmgt1_add_ext538_metric_set(perf);
    acmgt1_add_ext539_metric_set(perf);
    acmgt1_add_ext540_metric_set(perf);
    acmgt1_add_ext541_metric_set(perf);
    acmgt1_add_ext542_metric_set(perf);
    acmgt1_add_ext543_metric_set(perf);
    acmgt1_add_ext544_metric_set(perf);
    acmgt1_add_ext545_metric_set(perf);
    acmgt1_add_ext546_metric_set(perf);
    acmgt1_add_ext547_metric_set(perf);
    acmgt1_add_ext548_metric_set(perf);
    acmgt1_add_ext549_metric_set(perf);
    acmgt1_add_ext550_metric_set(perf);
    acmgt1_add_ext551_metric_set(perf);
    acmgt1_add_ext552_metric_set(perf);
    acmgt1_add_ext553_metric_set(perf);
    acmgt1_add_ext554_metric_set(perf);
    acmgt1_add_ext555_metric_set(perf);
    acmgt1_add_ext556_metric_set(perf);
    acmgt1_add_ext557_metric_set(perf);
    acmgt1_add_ext558_metric_set(perf);
    acmgt1_add_ext559_metric_set(perf);
    acmgt1_add_ext560_metric_set(perf);
    acmgt1_add_ext561_metric_set(perf);
    acmgt1_add_ext562_metric_set(perf);
    acmgt1_add_ext563_metric_set(perf);
    acmgt1_add_ext564_metric_set(perf);
    acmgt1_add_ext565_metric_set(perf);
    acmgt1_add_ext566_metric_set(perf);
    acmgt1_add_ext567_metric_set(perf);
    acmgt1_add_ext568_metric_set(perf);
    acmgt1_add_ext569_metric_set(perf);
    acmgt1_add_ext570_metric_set(perf);
    acmgt1_add_ext571_metric_set(perf);
    acmgt1_add_ext1000_metric_set(perf);
    acmgt1_add_ext1001_metric_set(perf);
    acmgt1_add_ext1002_metric_set(perf);
    acmgt1_add_ext1004_metric_set(perf);
    acmgt1_add_ext1005_metric_set(perf);
    acmgt1_add_ext1006_metric_set(perf);
    acmgt1_add_ext1007_metric_set(perf);
    acmgt1_add_ext1010_metric_set(perf);
}
