/* Autogenerated file, DO NOT EDIT manually! generated by perf-metricset-codegen.py
 *
 * Copyright (c) 2018 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include <assert.h>

#include "i915_drm.h"

#include "i915_perf_metrics_mtlgt3.h"
#include "i915_perf_equations.h"
#include "i915_perf_registers_mtlgt3.h"

static bool mtlgt3_render_basic_SamplerBottleneck_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & 1) {
        return true;
    }
    return false;
}
static bool mtlgt3_render_basic_SamplersBusy_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & 1) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_render_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics Basic";
    metric_set->symbol_name = "RenderBasic";
    metric_set->hw_config_guid = "1124d1b6-6182-4b5a-950b-27b38ef7c996";
    metric_set->counters = calloc(38, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_render_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__render_basic__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__render_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__render_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__render_basic__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "Early Depth Test Fails",
                .symbol_name = "EarlyDepthTestFails",
                .desc = "The total number of pixels dropped on early depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__render_basic__early_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Rasterizer/Early Depth Test",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__render_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__render_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__render_basic__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__render_basic__gti_read_throughput__read,
                .max_uint64 = mtlgt3__render_basic__gti_read_throughput__max,
                .group = "GTI",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__render_basic__gti_write_throughput__read,
                .max_uint64 = mtlgt3__render_basic__gti_write_throughput__max,
                .group = "GTI",
            },

            {
                .name = "Early Hi-Depth Test Fails",
                .symbol_name = "HiDepthTestFails",
                .desc = "The total number of pixels dropped on early hierarchical depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__render_basic__hi_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Rasterizer/Hi-Depth Test",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__render_basic__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "Pixels Failing Tests",
                .symbol_name = "PixelsFailingPostPsTests",
                .desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__render_basic__pixels_failing_post_ps_tests__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "FS Send Pipe Active",
                .symbol_name = "PsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__ps_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__render_basic__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "Rasterized Pixels",
                .symbol_name = "RasterizedPixels",
                .desc = "The total number of rasterized pixels.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__render_basic__rasterized_pixels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Rasterizer",
            },

            {
                .name = "Samplers Bottleneck",
                .symbol_name = "SamplerBottleneck",
                .desc = "The percentage of time in which samplers have been slowing down the pipe when processing XVE requests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__sampler_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = mtlgt3_render_basic_SamplerBottleneck_availability,
            },

            {
                .name = "Sampler Texels Misses",
                .symbol_name = "SamplerTexelMisses",
                .desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = mtlgt3__render_basic__sampler_texel_misses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler/Sampler Cache",
            },

            {
                .name = "Sampler Texels",
                .symbol_name = "SamplerTexels",
                .desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = mtlgt3__render_basic__sampler_texels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler/Sampler Input",
            },

            {
                .name = "Samplers Busy",
                .symbol_name = "SamplersBusy",
                .desc = "The percentage of time in which samplers or L1 cache are not idle.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__samplers_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "Sampler",
                .availability = mtlgt3_render_basic_SamplersBusy_availability,
            },

            {
                .name = "Samples Blended",
                .symbol_name = "SamplesBlended",
                .desc = "The total number of blended samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__render_basic__samples_blended__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "Samples Killed in FS",
                .symbol_name = "SamplesKilledInPs",
                .desc = "The total number of samples or pixels dropped in fragment shaders.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__render_basic__samples_killed_in_ps__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Fragment Shader",
            },

            {
                .name = "Samples Written",
                .symbol_name = "SamplesWritten",
                .desc = "The total number of samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__render_basic__samples_written__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__render_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3/Data Port/Atomics",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__render_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Barrier",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__render_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3/Data Port",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__render_basic__slm_reads__read,
                .max_uint64 = mtlgt3__render_basic__slm_reads__max,
                .group = "L3/Data Port/SLM",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__render_basic__slm_writes__read,
                .max_uint64 = mtlgt3__render_basic__slm_writes__max,
                .group = "L3/Data Port/SLM",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "VS Send Pipe Active",
                .symbol_name = "VsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__vs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__render_basic__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 38);
}


static void
mtlgt3_add_compute_basic_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Compute Metrics Basic";
    metric_set->symbol_name = "ComputeBasic";
    metric_set->hw_config_guid = "522743d7-4e01-461a-8600-7904e8ddc80c";
    metric_set->counters = calloc(39, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_compute_basic_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__compute_basic__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__compute_basic__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__compute_basic__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__compute_basic__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "Early Depth Test Fails",
                .symbol_name = "EarlyDepthTestFails",
                .desc = "The total number of pixels dropped on early depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__compute_basic__early_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Rasterizer/Early Depth Test",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__compute_basic__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__compute_basic__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__compute_basic__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "GTI Read Throughput",
                .symbol_name = "GtiReadThroughput",
                .desc = "The total number of GPU memory bytes read from GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__compute_basic__gti_read_throughput__read,
                .max_uint64 = mtlgt3__compute_basic__gti_read_throughput__max,
                .group = "GTI",
            },

            {
                .name = "GTI Write Throughput",
                .symbol_name = "GtiWriteThroughput",
                .desc = "The total number of GPU memory bytes written to GTI.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__compute_basic__gti_write_throughput__read,
                .max_uint64 = mtlgt3__compute_basic__gti_write_throughput__max,
                .group = "GTI",
            },

            {
                .name = "Early Hi-Depth Test Fails",
                .symbol_name = "HiDepthTestFails",
                .desc = "The total number of pixels dropped on early hierarchical depth test.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__compute_basic__hi_depth_test_fails__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Rasterizer/Hi-Depth Test",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__compute_basic__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "Pixels Failing Tests",
                .symbol_name = "PixelsFailingPostPsTests",
                .desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__compute_basic__pixels_failing_post_ps_tests__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__compute_basic__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "Rasterized Pixels",
                .symbol_name = "RasterizedPixels",
                .desc = "The total number of rasterized pixels.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__compute_basic__rasterized_pixels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Rasterizer",
            },

            {
                .name = "Sampler Texels Misses",
                .symbol_name = "SamplerTexelMisses",
                .desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = mtlgt3__compute_basic__sampler_texel_misses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler/Sampler Cache",
            },

            {
                .name = "Sampler Texels",
                .symbol_name = "SamplerTexels",
                .desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = mtlgt3__compute_basic__sampler_texels__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler/Sampler Input",
            },

            {
                .name = "Samples Blended",
                .symbol_name = "SamplesBlended",
                .desc = "The total number of blended samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__compute_basic__samples_blended__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "Samples Killed in FS",
                .symbol_name = "SamplesKilledInPs",
                .desc = "The total number of samples or pixels dropped in fragment shaders.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__compute_basic__samples_killed_in_ps__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Fragment Shader",
            },

            {
                .name = "Samples Written",
                .symbol_name = "SamplesWritten",
                .desc = "The total number of samples or pixels written to all render targets.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__compute_basic__samples_written__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "Send Pipe Active",
                .symbol_name = "SendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "Shader Atomic Memory Accesses",
                .symbol_name = "ShaderAtomics",
                .desc = "The total number of shader atomic memory accesses.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__compute_basic__shader_atomics__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3/Data Port/Atomics",
            },

            {
                .name = "Shader Barrier Messages",
                .symbol_name = "ShaderBarriers",
                .desc = "The total number of shader barrier messages.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__compute_basic__shader_barriers__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Barrier",
            },

            {
                .name = "Shader Memory Accesses",
                .symbol_name = "ShaderMemoryAccesses",
                .desc = "The total number of shader memory accesses to L3.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__compute_basic__shader_memory_accesses__read,
                .max_uint64 = NULL /* undefined */,
                .group = "L3/Data Port",
            },

            {
                .name = "SLM Bytes Read",
                .symbol_name = "SlmReads",
                .desc = "The total number of reads from shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__compute_basic__slm_reads__read,
                .max_uint64 = mtlgt3__compute_basic__slm_reads__max,
                .group = "L3/Data Port/SLM",
            },

            {
                .name = "SLM Writes",
                .symbol_name = "SlmWrites",
                .desc = "The total number of writes into shared local memory.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__compute_basic__slm_writes__read,
                .max_uint64 = mtlgt3__compute_basic__slm_writes__max,
                .group = "L3/Data Port/SLM",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__compute_basic__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XMX Pipe Active",
                .symbol_name = "XmxActive",
                .desc = "The percentage of time in which XVE XMX pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE AVG IPC Rate",
                .symbol_name = "XveAvgIpcRate",
                .desc = "The average rate of IPC calculated for 2 FPU pipelines.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NUMBER,
                .read_float = mtlgt3__compute_basic__xve_avg_ipc_rate__read,
                .max_float = mtlgt3__compute_basic__xve_avg_ipc_rate__max,
                .group = "EU Array",
            },

            {
                .name = "EM And FPU Pipes Active",
                .symbol_name = "XveFpuEmActive",
                .desc = "The percentage of time in which XVE EM INT and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_fpu_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "FPU FLT16 Instruction",
                .symbol_name = "XveFpuFlt16",
                .desc = "The percentage of time in which FLT16 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_fpu_flt16__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "FPU FLT32 Instruction",
                .symbol_name = "XveFpuFlt32",
                .desc = "The percentage of time in which FLT32 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_fpu_flt32__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "FPU FLT64 Instruction",
                .symbol_name = "XveFpuFlt64",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_fpu_flt64__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XMX And FPU Pipes Active",
                .symbol_name = "XveFpuXmxActive",
                .desc = "The percentage of time in which XVE XMX and FPU INT64 pipelines were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_fpu_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__compute_basic__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 39);
}


static void
mtlgt3_add_async_compute_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "AsyncCompute";
    metric_set->symbol_name = "AsyncCompute";
    metric_set->hw_config_guid = "d9edd254-60e8-4ce0-82b1-7b3de3bc79a6";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_async_compute_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC CS EM Pipe Active",
                .symbol_name = "AsyncCsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__async_cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "ASYNC CS FPU Pipe Active",
                .symbol_name = "AsyncCsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__async_cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__async_compute__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__async_compute__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS EM Pipe Active",
                .symbol_name = "CsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__cs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "CS FPU Pipe Active",
                .symbol_name = "CsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__cs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__async_compute__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__async_compute__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "EM Pipe Active",
                .symbol_name = "EmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE FPU Pipe Active",
                .symbol_name = "FpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__async_compute__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__async_compute__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__async_compute__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__async_compute__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "FS EM Pipe Active",
                .symbol_name = "PsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__ps_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "FS FPU Pipe Active",
                .symbol_name = "PsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a fragment shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__ps_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__async_compute__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "VS EM Pipe Active",
                .symbol_name = "VsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__vs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "VS FPU Pipe Active",
                .symbol_name = "VsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a vertex shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__vs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__async_compute__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__async_compute__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
mtlgt3_add_xve_activity_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "XveActivity";
    metric_set->symbol_name = "XveActivity";
    metric_set->hw_config_guid = "703a9693-1444-4e7c-a235-1c4d6ee01943";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_xve_activity_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__xve_activity__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__xve_activity__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CS Send Pipe Active",
                .symbol_name = "CsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a compute shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__cs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__xve_activity__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "DS EM Pipe Active",
                .symbol_name = "DsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__ds_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "DS FPU Pipe Active",
                .symbol_name = "DsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__ds_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "DS Send Pipe Active",
                .symbol_name = "DsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a domain shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__ds_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__xve_activity__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__xve_activity__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__xve_activity__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS EM Pipe Active",
                .symbol_name = "GsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__gs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "GS FPU Pipe Active",
                .symbol_name = "GsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__gs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "GS Send Pipe Active",
                .symbol_name = "GsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a geometry shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__gs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__xve_activity__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "HS EM Pipe Active",
                .symbol_name = "HsEmActive",
                .desc = "The percentage of time in which XVE EM INT pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__hs_em_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "HS FPU Pipe Active",
                .symbol_name = "HsFpuActive",
                .desc = "The percentage of time in which XVE FPU INT64 pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__hs_fpu_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "HS Send Pipe Active",
                .symbol_name = "HsSendActive",
                .desc = "The percentage of time in which XVE send pipeline was actively processing a hull shader instruction.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__xve_activity__hs_send_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__xve_activity__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__xve_activity__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__xve_activity__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Vertex Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
mtlgt3_add_gpu_busyness_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "GpuBusyness";
    metric_set->symbol_name = "GpuBusyness";
    metric_set->hw_config_guid = "edae72d3-bb06-47af-87b4-7585274c6076";
    metric_set->counters = calloc(16, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_gpu_busyness_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__gpu_busyness__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__gpu_busyness__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "Blitter Ring Busy",
                .symbol_name = "BlitterBusy",
                .desc = "The percentage of time when blitter command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__gpu_busyness__blitter_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "ComputeEngine0 Ring Busy",
                .symbol_name = "ComputeEngine0Busy",
                .desc = "The percentage of time when compute command streamer 0 was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__gpu_busyness__compute_engine0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "CS Threads Dispatched",
                .symbol_name = "CsThreads",
                .desc = "The total number of compute shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__gpu_busyness__cs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "DS Threads Dispatched",
                .symbol_name = "DsThreads",
                .desc = "The total number of domain shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__gpu_busyness__ds_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__gpu_busyness__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__gpu_busyness__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__gpu_busyness__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS Threads Dispatched",
                .symbol_name = "GsThreads",
                .desc = "The total number of geometry shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__gpu_busyness__gs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "HS Threads Dispatched",
                .symbol_name = "HsThreads",
                .desc = "The total number of hull shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__gpu_busyness__hs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "FS Threads Dispatched",
                .symbol_name = "PsThreads",
                .desc = "The total number of fragment shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__gpu_busyness__ps_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "Render Ring Busy",
                .symbol_name = "RenderBusy",
                .desc = "The percentage of time when render command streamer was busy.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__gpu_busyness__render_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "VS Threads Dispatched",
                .symbol_name = "VsThreads",
                .desc = "The total number of vertex shader hardware threads dispatched.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_THREADS,
                .read_uint64 = mtlgt3__gpu_busyness__vs_threads__read,
                .max_uint64 = NULL /* undefined */,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE Active",
                .symbol_name = "XveActive",
                .desc = "The percentage of time in which the Execution Units were actively processing.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__gpu_busyness__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE Stall",
                .symbol_name = "XveStall",
                .desc = "The percentage of time in which the Execution Units were stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__gpu_busyness__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE Thread Occupancy",
                .symbol_name = "XveThreadOccupancy",
                .desc = "The percentage of time in which hardware threads occupied XVEs.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__gpu_busyness__xve_thread_occupancy__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 16);
}

static bool mtlgt3_hdc_and_sf1_NonSamplerShader00AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_hdc_and_sf1_NonSamplerShader01AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_hdc_and_sf1_NonSamplerShader02AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_hdc_and_sf1_NonSamplerShader03AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_hdc_and_sf1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF1";
    metric_set->symbol_name = "HDCAndSF1";
    metric_set->hw_config_guid = "e1a408d6-aece-4bde-8bbd-1c7fbfff02cf";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_hdc_and_sf1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__hdc_and_sf1__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__hdc_and_sf1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__hdc_and_sf1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__hdc_and_sf1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice0 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader00AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf1__non_sampler_shader00_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf1_NonSamplerShader00AccessStalledOnL3_availability,
            },

            {
                .name = "Slice0 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader01AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf1__non_sampler_shader01_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf1_NonSamplerShader01AccessStalledOnL3_availability,
            },

            {
                .name = "Slice0 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader02AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf1__non_sampler_shader02_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf1_NonSamplerShader02AccessStalledOnL3_availability,
            },

            {
                .name = "Slice0 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader03AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf1__non_sampler_shader03_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf1_NonSamplerShader03AccessStalledOnL3_availability,
            },

            {
                .name = "Polygon (Slice0) Data Ready",
                .symbol_name = "Poly0DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf1__poly0_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/3D Pipe/Strip-Fans",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool mtlgt3_hdc_and_sf2_NonSamplerShader10AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_hdc_and_sf2_NonSamplerShader11AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_hdc_and_sf2_NonSamplerShader12AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_hdc_and_sf2_NonSamplerShader13AccessStalledOnL3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_hdc_and_sf2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set HDCAndSF2";
    metric_set->symbol_name = "HDCAndSF2";
    metric_set->hw_config_guid = "374e8aa3-09df-4d69-ad32-3133f6ad3c86";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_hdc_and_sf2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__hdc_and_sf2__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__hdc_and_sf2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__hdc_and_sf2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__hdc_and_sf2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice1 Xe Core0 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader10AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core0)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf2__non_sampler_shader10_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf2_NonSamplerShader10AccessStalledOnL3_availability,
            },

            {
                .name = "Slice1 Xe Core1 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader11AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core1)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf2__non_sampler_shader11_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf2_NonSamplerShader11AccessStalledOnL3_availability,
            },

            {
                .name = "Slice1 Xe Core2 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader12AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core2)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf2__non_sampler_shader12_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf2_NonSamplerShader12AccessStalledOnL3_availability,
            },

            {
                .name = "Slice1 Xe Core3 Non-sampler Shader Access Stalled On L3",
                .symbol_name = "NonSamplerShader13AccessStalledOnL3",
                .desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Xe Core3)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf2__non_sampler_shader13_access_stalled_on_l3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Data Port",
                .availability = mtlgt3_hdc_and_sf2_NonSamplerShader13AccessStalledOnL3_availability,
            },

            {
                .name = "Polygon (Slice1) Data Ready",
                .symbol_name = "Poly1DataReady",
                .desc = "The percentage of time in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__hdc_and_sf2__poly1_data_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/3D Pipe/Strip-Fans",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_l3_L3_OUTPUT_READY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_l3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "L3";
    metric_set->symbol_name = "L3";
    metric_set->hw_config_guid = "580d5311-4e9d-4210-b419-37259ffcd3f2";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_l3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__l3__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__l3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__l3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__l3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK0",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK0",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK0_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK1",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK1",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK1_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK2",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK2",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK2_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK3",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK3",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK3_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK4",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK4",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK4_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK5",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK5",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK5_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK6",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK6",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK6_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK7",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK7",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_input_available_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_INPUT_AVAILABLE_L3BANK7_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK0",
                .symbol_name = "L3_OUTPUT_READY_L3BANK0",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK0_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK1",
                .symbol_name = "L3_OUTPUT_READY_L3BANK1",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK1_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK2",
                .symbol_name = "L3_OUTPUT_READY_L3BANK2",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK2_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK3",
                .symbol_name = "L3_OUTPUT_READY_L3BANK3",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK3_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK4",
                .symbol_name = "L3_OUTPUT_READY_L3BANK4",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK4_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK5",
                .symbol_name = "L3_OUTPUT_READY_L3BANK5",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK5_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK6",
                .symbol_name = "L3_OUTPUT_READY_L3BANK6",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK6_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK7",
                .symbol_name = "L3_OUTPUT_READY_L3BANK7",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__l3__l3_output_ready_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_l3_L3_OUTPUT_READY_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool mtlgt3_rasterizer_and_pixel_backend1_Rasterizer0InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_rasterizer_and_pixel_backend1_Rasterizer1InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_rasterizer_and_pixel_backend1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend1";
    metric_set->symbol_name = "RasterizerAndPixelBackend1";
    metric_set->hw_config_guid = "4286bd8f-f9db-45e5-aa37-51dd7067f751";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_rasterizer_and_pixel_backend1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__rasterizer_and_pixel_backend1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__rasterizer_and_pixel_backend1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__rasterizer_and_pixel_backend1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice0 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData00Ready",
                .desc = "The percentage of time in which slice0  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend1__pixel_data00_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer/Early Depth Test",
            },

            {
                .name = "Slice0 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData01Ready",
                .desc = "The percentage of time in which slice0  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend1__pixel_data01_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer/Early Depth Test",
            },

            {
                .name = "Slice1 Pipe0 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData10Ready",
                .desc = "The percentage of time in which slice1  pipe0 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend1__pixel_data10_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer/Early Depth Test",
            },

            {
                .name = "Slice1 Pipe1 Post-EarlyZ Pixel Data Ready",
                .symbol_name = "PixelData11Ready",
                .desc = "The percentage of time in which slice1  pipe1 post-EarlyZ pixel data is ready (after early Z tests have been applied)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend1__pixel_data11_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer/Early Depth Test",
            },

            {
                .name = "Slice0 Rasterizer Input Available",
                .symbol_name = "Rasterizer0InputAvailable",
                .desc = "The percentage of time in which slice0 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend1__rasterizer0_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer",
                .availability = mtlgt3_rasterizer_and_pixel_backend1_Rasterizer0InputAvailable_availability,
            },

            {
                .name = "Slice1 Rasterizer Input Available",
                .symbol_name = "Rasterizer1InputAvailable",
                .desc = "The percentage of time in which slice1 rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend1__rasterizer1_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer",
                .availability = mtlgt3_rasterizer_and_pixel_backend1_Rasterizer1InputAvailable_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_rasterizer_and_pixel_backend2_Rasterizer0OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_rasterizer_and_pixel_backend2_Rasterizer1OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_rasterizer_and_pixel_backend2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set RasterizerAndPixelBackend2";
    metric_set->symbol_name = "RasterizerAndPixelBackend2";
    metric_set->hw_config_guid = "ac90f98d-14a6-4dcc-b5d7-31ee157bb6e2";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_rasterizer_and_pixel_backend2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__rasterizer_and_pixel_backend2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__rasterizer_and_pixel_backend2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__rasterizer_and_pixel_backend2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS00 Output Available",
                .symbol_name = "PSOutput00Available",
                .desc = "The percentage of time in which PS00 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend2__ps_output00_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/3D Pipe",
            },

            {
                .name = "PS01 Output Available",
                .symbol_name = "PSOutput01Available",
                .desc = "The percentage of time in which PS01 output is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend2__ps_output01_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/3D Pipe",
            },

            {
                .name = "Pixel Values 00 Ready",
                .symbol_name = "PixelValues00Ready",
                .desc = "The percentage of time in which pixel values 00 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend2__pixel_values00_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/3D Pipe",
            },

            {
                .name = "Pixel Values 01 Ready",
                .symbol_name = "PixelValues01Ready",
                .desc = "The percentage of time in which pixel values 01 are ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend2__pixel_values01_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/3D Pipe",
            },

            {
                .name = "Slice0 Rasterizer Output Ready",
                .symbol_name = "Rasterizer0OutputReady",
                .desc = "The percentage of time in which slice0 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend2__rasterizer0_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer",
                .availability = mtlgt3_rasterizer_and_pixel_backend2_Rasterizer0OutputReady_availability,
            },

            {
                .name = "Slice1 Rasterizer Output Ready",
                .symbol_name = "Rasterizer1OutputReady",
                .desc = "The percentage of time in which slice1 rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__rasterizer_and_pixel_backend2__rasterizer1_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Rasterizer",
                .availability = mtlgt3_rasterizer_and_pixel_backend2_Rasterizer1OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
mtlgt3_add_render_pipe_profile1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile1";
    metric_set->hw_config_guid = "f15b97f6-eb1b-43a8-839c-7bd956c143c4";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_render_pipe_profile1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__render_pipe_profile1__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__render_pipe_profile1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC00 Bottleneck",
                .symbol_name = "Bc00Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__bc00_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Barycentric Calc",
            },

            {
                .name = "Clipper0 Bottleneck",
                .symbol_name = "Cl0Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__cl0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Clipper",
            },

            {
                .name = "CL0 Stall",
                .symbol_name = "Cl0Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__cl0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Clipper",
            },

            {
                .name = "DS0 Bottleneck",
                .symbol_name = "Ds0Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__ds0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Domain Shader",
            },

            {
                .name = "DS0 Stall",
                .symbol_name = "Ds0Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__ds0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Domain Shader",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__render_pipe_profile1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__render_pipe_profile1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS0 Bottleneck",
                .symbol_name = "Gs0Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__gs0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Geometry Shader",
            },

            {
                .name = "Hi-Depth00 Bottleneck",
                .symbol_name = "HiDepth00Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__hi_depth00_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Hi-Depth Test",
            },

            {
                .name = "Hi-Depth01 Bottleneck",
                .symbol_name = "HiDepth01Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__hi_depth01_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Hi-Depth Test",
            },

            {
                .name = "HS0 Bottleneck",
                .symbol_name = "Hs0Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__hs0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Hull Shader",
            },

            {
                .name = "HS0 Stall",
                .symbol_name = "Hs0Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__hs0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Hull Shader",
            },

            {
                .name = "SF0 Bottleneck",
                .symbol_name = "Sf0Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__sf0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Strip-Fans",
            },

            {
                .name = "SF0 Stall",
                .symbol_name = "Sf0Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__sf0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Strip-Fans",
            },

            {
                .name = "SO0 Bottleneck",
                .symbol_name = "So0Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__so0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Stream Output",
            },

            {
                .name = "SO0 Stall",
                .symbol_name = "So0Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__so0_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Stream Output",
            },

            {
                .name = "VF0 Bottleneck",
                .symbol_name = "Vf0Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__vf0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Input Assembler",
            },

            {
                .name = "VS0 Bottleneck",
                .symbol_name = "Vs0Bottleneck",
                .desc = "The percentage of time in which VS0 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile1__vs0_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Vertex Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}


static void
mtlgt3_add_render_pipe_profile2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Render Metrics for 3D Pipeline Profile";
    metric_set->symbol_name = "RenderPipeProfile2";
    metric_set->hw_config_guid = "86b9199d-8a44-4694-bbde-6fd35bada236";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_render_pipe_profile2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__render_pipe_profile2__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__render_pipe_profile2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "BC10 Bottleneck",
                .symbol_name = "Bc10Bottleneck",
                .desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__bc10_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Barycentric Calc",
            },

            {
                .name = "Clipper1 Bottleneck",
                .symbol_name = "Cl1Bottleneck",
                .desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__cl1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Clipper",
            },

            {
                .name = "CL1 Stall",
                .symbol_name = "Cl1Stall",
                .desc = "The percentage of time in which clipper pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__cl1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Clipper",
            },

            {
                .name = "DS1 Bottleneck",
                .symbol_name = "Ds1Bottleneck",
                .desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__ds1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Domain Shader",
            },

            {
                .name = "DS1 Stall",
                .symbol_name = "Ds1Stall",
                .desc = "The percentage of time in which domain shader pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__ds1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Domain Shader",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__render_pipe_profile2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__render_pipe_profile2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GS1 Bottleneck",
                .symbol_name = "Gs1Bottleneck",
                .desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__gs1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Geometry Shader",
            },

            {
                .name = "Hi-Depth10 Bottleneck",
                .symbol_name = "HiDepth10Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__hi_depth10_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Hi-Depth Test",
            },

            {
                .name = "Hi-Depth11 Bottleneck",
                .symbol_name = "HiDepth11Bottleneck",
                .desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__hi_depth11_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Hi-Depth Test",
            },

            {
                .name = "HS1 Bottleneck",
                .symbol_name = "Hs1Bottleneck",
                .desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__hs1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Hull Shader",
            },

            {
                .name = "HS1 Stall",
                .symbol_name = "Hs1Stall",
                .desc = "The percentage of time in which hull stall pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__hs1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Hull Shader",
            },

            {
                .name = "SF1 Bottleneck",
                .symbol_name = "Sf1Bottleneck",
                .desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__sf1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Strip-Fans",
            },

            {
                .name = "SF1 Stall",
                .symbol_name = "Sf1Stall",
                .desc = "The percentage of time in which strip-fans pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__sf1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Rasterizer/Strip-Fans",
            },

            {
                .name = "SO1 Bottleneck",
                .symbol_name = "So1Bottleneck",
                .desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__so1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Stream Output",
            },

            {
                .name = "SO1 Stall",
                .symbol_name = "So1Stall",
                .desc = "The percentage of time in which stream-output pipeline stage was stalled.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__so1_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Stream Output",
            },

            {
                .name = "VF1 Bottleneck",
                .symbol_name = "Vf1Bottleneck",
                .desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__vf1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Input Assembler",
            },

            {
                .name = "VS1 Bottleneck",
                .symbol_name = "Vs1Bottleneck",
                .desc = "The percentage of time in which VS1 pipeline stage was slowing down the 3D pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__render_pipe_profile2__vs1_bottleneck__read,
                .max_float = percentage_max_callback_float,
                .group = "3D Pipe/Vertex Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool mtlgt3_sampler_Sampler00InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler00OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler01InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler01OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler02InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler02OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler03InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler03OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler10InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler10OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler11InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler11OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler12InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler12OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler13InputAvailable_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_sampler_Sampler13OutputReady_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_sampler_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Sampler_Slice0";
    metric_set->symbol_name = "Sampler";
    metric_set->hw_config_guid = "ae70a69c-341d-492a-b703-afa08a3497ba";
    metric_set->counters = calloc(20, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_sampler_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__sampler__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__sampler__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__sampler__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__sampler__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Slice0 Xe Core0 Input Available",
                .symbol_name = "Sampler00InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler00_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler00InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler00OutputReady",
                .desc = "The percentage of time in which slice0 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler00_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler00OutputReady_availability,
            },

            {
                .name = "Slice0 Xe Core1 Input Available",
                .symbol_name = "Sampler01InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler01_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler01InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler01OutputReady",
                .desc = "The percentage of time in which slice0 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler01_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler01OutputReady_availability,
            },

            {
                .name = "Slice0 Xe Core2 Input Available",
                .symbol_name = "Sampler02InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler02_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler02InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler02OutputReady",
                .desc = "The percentage of time in which slice0 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler02_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler02OutputReady_availability,
            },

            {
                .name = "Slice0 Xe Core3 Input Available",
                .symbol_name = "Sampler03InputAvailable",
                .desc = "The percentage of time in which slice0 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler03_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler03InputAvailable_availability,
            },

            {
                .name = "Slice0 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler03OutputReady",
                .desc = "The percentage of time in which slice0 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler03_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler03OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core0 Input Available",
                .symbol_name = "Sampler10InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core0 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler10_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler10InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core0 Sampler Output Ready",
                .symbol_name = "Sampler10OutputReady",
                .desc = "The percentage of time in which slice1 Xe core0 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler10_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler10OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core1 Input Available",
                .symbol_name = "Sampler11InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core1 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler11_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler11InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core1 Sampler Output Ready",
                .symbol_name = "Sampler11OutputReady",
                .desc = "The percentage of time in which slice1 Xe core1 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler11_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler11OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core2 Input Available",
                .symbol_name = "Sampler12InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core2 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler12_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler12InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core2 Sampler Output Ready",
                .symbol_name = "Sampler12OutputReady",
                .desc = "The percentage of time in which slice1 Xe core2 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler12_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler12OutputReady_availability,
            },

            {
                .name = "Slice1 Xe Core3 Input Available",
                .symbol_name = "Sampler13InputAvailable",
                .desc = "The percentage of time in which slice1 Xe core3 sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler13_input_available__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler13InputAvailable_availability,
            },

            {
                .name = "Slice1 Xe Core3 Sampler Output Ready",
                .symbol_name = "Sampler13OutputReady",
                .desc = "The percentage of time in which slice1 Xe core3 sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__sampler__sampler13_output_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Sampler",
                .availability = mtlgt3_sampler_Sampler13OutputReady_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 20);
}

static bool mtlgt3_tdl1_NonPSThread00ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_NonPSThread01ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_PSThread00ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_PSThread01ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader00Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader00ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader00ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader00ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader00ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader01Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader01ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader01ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader01ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl1_ThreadHeader01ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_tdl1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL1";
    metric_set->symbol_name = "TDL1";
    metric_set->hw_config_guid = "cf27081a-d750-4c9d-8a19-154f976992ee";
    metric_set->counters = calloc(18, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_tdl1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__tdl1__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__tdl1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__tdl1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__tdl1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread00ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__non_ps_thread00_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_NonPSThread00ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread01ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__non_ps_thread01_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_NonPSThread01ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread00ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__ps_thread00_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_PSThread00ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread01ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__ps_thread01_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_PSThread01ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader00Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header00_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader00Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader00ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header00_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader00ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader00ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header00_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader00ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader00ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header00_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader00ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader00ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header00_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader00ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader01Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header01_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader01Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader01ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header01_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader01ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader01ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header01_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader01ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader01ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header01_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader01ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader01ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl1__thread_header01_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl1_ThreadHeader01ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 18);
}

static bool mtlgt3_tdl2_NonPSThread02ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_NonPSThread03ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_PSThread02ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_PSThread03ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader02Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader02ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader02ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader02ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader02ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader03Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader03ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader03ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader03ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl2_ThreadHeader03ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_tdl2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL2";
    metric_set->symbol_name = "TDL2";
    metric_set->hw_config_guid = "fa292653-8b18-448b-b57e-8e8ff92fac11";
    metric_set->counters = calloc(18, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_tdl2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__tdl2__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__tdl2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__tdl2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__tdl2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread02ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__non_ps_thread02_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_NonPSThread02ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread03ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__non_ps_thread03_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_NonPSThread03ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread02ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__ps_thread02_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_PSThread02ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice0 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread03ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice0 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__ps_thread03_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_PSThread03ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader02Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header02_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader02Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader02ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header02_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader02ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader02ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header02_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader02ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader02ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header02_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader02ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader02ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header02_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader02ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader03Ready",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header03_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader03Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader03ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header03_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader03ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader03ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header03_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader03ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader03ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header03_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader03ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice0 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader03ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice0 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl2__thread_header03_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl2_ThreadHeader03ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 18);
}

static bool mtlgt3_tdl3_NonPSThread10ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_NonPSThread11ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_PSThread10ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_PSThread11ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader10Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader10ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader10ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader10ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader10ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader11Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader11ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader11ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader11ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl3_ThreadHeader11ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_tdl3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL3";
    metric_set->symbol_name = "TDL3";
    metric_set->hw_config_guid = "9604dfeb-2724-459c-a25b-5e5e06d93fd8";
    metric_set->counters = calloc(18, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_tdl3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__tdl3__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__tdl3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__tdl3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__tdl3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher",
                .symbol_name = "NonPSThread10ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__non_ps_thread10_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_NonPSThread10ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher",
                .symbol_name = "NonPSThread11ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__non_ps_thread11_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_NonPSThread11ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core0 Thread Dispatcher",
                .symbol_name = "PSThread10ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__ps_thread10_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_PSThread10ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core1 Thread Dispatcher",
                .symbol_name = "PSThread11ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__ps_thread11_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_PSThread11ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher",
                .symbol_name = "ThreadHeader10Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header10_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader10Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader10ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header10_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader10ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader10ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header10_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader10ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader10ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header10_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader10ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core0 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader10ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core0 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header10_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader10ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher",
                .symbol_name = "ThreadHeader11Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header11_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader11Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader11ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header11_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader11ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader11ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header11_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader11ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader11ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header11_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader11ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core1 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader11ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core1 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl3__thread_header11_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl3_ThreadHeader11ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 18);
}

static bool mtlgt3_tdl4_NonPSThread12ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_NonPSThread13ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_PSThread12ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_PSThread13ReadyForDispatch_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader12Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader12ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader12ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader12ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader12ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader13Ready_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader13ReadyPort0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader13ReadyPort1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader13ReadyPort2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_tdl4_ThreadHeader13ReadyPort3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_tdl4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TDL4";
    metric_set->symbol_name = "TDL4";
    metric_set->hw_config_guid = "b5333a47-add0-46a5-82d9-e62dcee14e81";
    metric_set->counters = calloc(18, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_tdl4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__tdl4__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__tdl4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Busy",
                .symbol_name = "GpuBusy",
                .desc = "The percentage of time in which the GPU has been processing GPU commands.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__gpu_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__tdl4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__tdl4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher",
                .symbol_name = "NonPSThread12ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__non_ps_thread12_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_NonPSThread12ReadyForDispatch_availability,
            },

            {
                .name = "Non-PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher",
                .symbol_name = "NonPSThread13ReadyForDispatch",
                .desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__non_ps_thread13_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_NonPSThread13ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core2 Thread Dispatcher",
                .symbol_name = "PSThread12ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__ps_thread12_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_PSThread12ReadyForDispatch_availability,
            },

            {
                .name = "PS Thread Ready For Dispatch on Slice1 Xe Core3 Thread Dispatcher",
                .symbol_name = "PSThread13ReadyForDispatch",
                .desc = "The percentage of time in which PS thread is ready for dispatch on slice1 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__ps_thread13_ready_for_dispatch__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_PSThread13ReadyForDispatch_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher",
                .symbol_name = "ThreadHeader12Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header12_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader12Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader12ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header12_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader12ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader12ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header12_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader12ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader12ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header12_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader12ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core2 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader12ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core2 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header12_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader12ReadyPort3_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher",
                .symbol_name = "ThreadHeader13Ready",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header13_ready__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader13Ready_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 0",
                .symbol_name = "ThreadHeader13ReadyPort0",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header13_ready_port0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader13ReadyPort0_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 1",
                .symbol_name = "ThreadHeader13ReadyPort1",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header13_ready_port1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader13ReadyPort1_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 2",
                .symbol_name = "ThreadHeader13ReadyPort2",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 2",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header13_ready_port2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader13ReadyPort2_availability,
            },

            {
                .name = "Thread Header Ready on Slice1 Xe Core3 Thread Dispatcher Port 3",
                .symbol_name = "ThreadHeader13ReadyPort3",
                .desc = "The percentage of time in which thread header is ready on slice1 Xe core3 thread dispatcher port 3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__tdl4__thread_header13_ready_port3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU/Thread Dispatcher",
                .availability = mtlgt3_tdl4_ThreadHeader13ReadyPort3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 18);
}


static void
mtlgt3_add_test_oa_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Metric set TestOa";
    metric_set->symbol_name = "TestOa";
    metric_set->hw_config_guid = "7272a7b8-6df2-4180-a95f-2ef7ad4412cc";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_test_oa_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__test_oa__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__test_oa__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "TestCounter0",
                .symbol_name = "Counter0",
                .desc = "HW test counter 0. Factor: 0.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter1",
                .symbol_name = "Counter1",
                .desc = "HW test counter 1. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter2",
                .symbol_name = "Counter2",
                .desc = "HW test counter 2. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter3",
                .symbol_name = "Counter3",
                .desc = "HW test counter 3. Factor: 0.5",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter4",
                .symbol_name = "Counter4",
                .desc = "HW test counter 4. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter5",
                .symbol_name = "Counter5",
                .desc = "HW test counter 5. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter6",
                .symbol_name = "Counter6",
                .desc = "HW test counter 6. Factor: 0.16666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter7",
                .symbol_name = "Counter7",
                .desc = "HW test counter 7. Factor: 0.6666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter8",
                .symbol_name = "Counter8",
                .desc = "HW test counter 8. Should be equal to 1 in IOStream or in OAG query mode",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TestCounter9 - OAR enable",
                .symbol_name = "Counter9",
                .desc = "HW test counter 9. Should be equal to 1 in query.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oa__counter9__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__test_oa__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__test_oa__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}


static void
mtlgt3_add_ext1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1";
    metric_set->symbol_name = "Ext1";
    metric_set->hw_config_guid = "682c3520-dffc-4a76-8e17-1d9effc01a1a";
    metric_set->counters = calloc(21, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI0",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI0",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1__gpu_memory_active_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY ACTIVE SQIDI1",
                .symbol_name = "GPU_MEMORY_ACTIVE_SQIDI1",
                .desc = "Percentage of time in which device local memory (HBM, GDDR, LPDDR, etc.) is active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1__gpu_memory_active_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = mtlgt3__ext1__gpu_memory_byte_read_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) read bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = mtlgt3__ext1__gpu_memory_byte_read_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_byte_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE READ SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) read bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_byte_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI0",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = mtlgt3__ext1__gpu_memory_byte_write_bw_sqidi0__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE WRITE BW SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_BW_SQIDI1",
                .desc = "Device local memory (HBM, GDDR, LPDDR, etc.) write bandwidth",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_GBPS,
                .read_float = mtlgt3__ext1__gpu_memory_byte_write_bw_sqidi1__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_byte_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY BYTE WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_BYTE_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) write bytes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_byte_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY READ",
                .symbol_name = "GPU_MEMORY_READ",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY READ SQIDI0",
                .symbol_name = "GPU_MEMORY_READ_SQIDI0",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY READ SQIDI1",
                .symbol_name = "GPU_MEMORY_READ_SQIDI1",
                .desc = "Number of GTI memory reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI0",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI0",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1__gpu_memory_request_queue_full_sqidi0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY REQUEST QUEUE FULL SQIDI1",
                .symbol_name = "GPU_MEMORY_REQUEST_QUEUE_FULL_SQIDI1",
                .desc = "Percentage of time in which SQ is filled above a threshold (usually 48 entries)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1__gpu_memory_request_queue_full_sqidi1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY WRITE",
                .symbol_name = "GPU_MEMORY_WRITE",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1__gpu_memory_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 21);
}


static void
mtlgt3_add_ext3_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext3";
    metric_set->symbol_name = "Ext3";
    metric_set->hw_config_guid = "b24b7052-70a1-4ef7-b61d-7ee4d7e159ab";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext3_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext3__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext3__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_32_b_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_32_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_32_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_32_b_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_32_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 32B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_32B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (32B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_32_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_64_b_transaction_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_64_b_transaction_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION READ SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_READ_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) reads (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_64_b_transaction_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_64_b_transaction_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI0",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_64_b_transaction_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY 64B TRANSACTION WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_64B_TRANSACTION_WRITE_SQIDI1",
                .desc = "Number of device local memory (HBM, GDDR, LPDDR, etc.) writes (64B)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext3__gpu_memory_64_b_transaction_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext3__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext3__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

static bool mtlgt3_ext4_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext4_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext4_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext4";
    metric_set->symbol_name = "Ext4";
    metric_set->hw_config_guid = "205ab9ab-56fd-4fdc-b3b3-91dc57be0fd3";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext4_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext4__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext4__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext4__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext4__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 READ L3BANK0",
                .symbol_name = "L3_READ_L3BANK0",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK0_availability,
            },

            {
                .name = "L3 READ L3BANK1",
                .symbol_name = "L3_READ_L3BANK1",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK1_availability,
            },

            {
                .name = "L3 READ L3BANK2",
                .symbol_name = "L3_READ_L3BANK2",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK2_availability,
            },

            {
                .name = "L3 READ L3BANK3",
                .symbol_name = "L3_READ_L3BANK3",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK3_availability,
            },

            {
                .name = "L3 READ L3BANK4",
                .symbol_name = "L3_READ_L3BANK4",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK4_availability,
            },

            {
                .name = "L3 READ L3BANK5",
                .symbol_name = "L3_READ_L3BANK5",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK5_availability,
            },

            {
                .name = "L3 READ L3BANK6",
                .symbol_name = "L3_READ_L3BANK6",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK6_availability,
            },

            {
                .name = "L3 READ L3BANK7",
                .symbol_name = "L3_READ_L3BANK7",
                .desc = "Number of L3 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext4_L3_READ_L3BANK7_availability,
            },

            {
                .name = "L3 WRITE L3BANK0",
                .symbol_name = "L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "L3 WRITE L3BANK1",
                .symbol_name = "L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "L3 WRITE L3BANK2",
                .symbol_name = "L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "L3 WRITE L3BANK3",
                .symbol_name = "L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "L3 WRITE L3BANK4",
                .symbol_name = "L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "L3 WRITE L3BANK5",
                .symbol_name = "L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "L3 WRITE L3BANK6",
                .symbol_name = "L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "L3 WRITE L3BANK7",
                .symbol_name = "L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext4__l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext4_L3_WRITE_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext5_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext5";
    metric_set->symbol_name = "Ext5";
    metric_set->hw_config_guid = "26cb7ee1-a26d-410a-9283-e07d6ced5fce";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext5_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext5__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext5__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT L3 READ L3BANK0",
                .symbol_name = "DATAPORT_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK1",
                .symbol_name = "DATAPORT_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK2",
                .symbol_name = "DATAPORT_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK3",
                .symbol_name = "DATAPORT_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK4",
                .symbol_name = "DATAPORT_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK5",
                .symbol_name = "DATAPORT_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK6",
                .symbol_name = "DATAPORT_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 READ L3BANK7",
                .symbol_name = "DATAPORT_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_READ_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK0",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK0",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK1",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK1",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK2",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK2",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK3",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK3",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK4",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK4",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK5",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK5",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK6",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK6",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 WRITE L3BANK7",
                .symbol_name = "DATAPORT_L3_WRITE_L3BANK7",
                .desc = "Number of L3 write requests coming from XVE via Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext5__dataport_l3_write_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext5_DATAPORT_L3_WRITE_L3BANK7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext5__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext5__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext6_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext6_SAMPLER_BUSY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext6_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext6";
    metric_set->symbol_name = "Ext6";
    metric_set->hw_config_guid = "e62c9cd7-ada7-487d-87aa-b1ad4ab9a2c5";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext6_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext6__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext6__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext6__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext6__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 HIT L3BANK0",
                .symbol_name = "L3_HIT_L3BANK0",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "L3 HIT L3BANK1",
                .symbol_name = "L3_HIT_L3BANK1",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "L3 HIT L3BANK2",
                .symbol_name = "L3_HIT_L3BANK2",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "L3 HIT L3BANK3",
                .symbol_name = "L3_HIT_L3BANK3",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "L3 HIT L3BANK4",
                .symbol_name = "L3_HIT_L3BANK4",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "L3 HIT L3BANK5",
                .symbol_name = "L3_HIT_L3BANK5",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "L3 HIT L3BANK6",
                .symbol_name = "L3_HIT_L3BANK6",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "L3 HIT L3BANK7",
                .symbol_name = "L3_HIT_L3BANK7",
                .desc = "Number of L3 accesses which hits in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext6__l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext6_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE0",
                .symbol_name = "SAMPLER_BUSY_XECORE0",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE0_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE1",
                .symbol_name = "SAMPLER_BUSY_XECORE1",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE1_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE2",
                .symbol_name = "SAMPLER_BUSY_XECORE2",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE2_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE3",
                .symbol_name = "SAMPLER_BUSY_XECORE3",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE3_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE4",
                .symbol_name = "SAMPLER_BUSY_XECORE4",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE4_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE5",
                .symbol_name = "SAMPLER_BUSY_XECORE5",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE5_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE6",
                .symbol_name = "SAMPLER_BUSY_XECORE6",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE6_availability,
            },

            {
                .name = "SAMPLER BUSY XECORE7",
                .symbol_name = "SAMPLER_BUSY_XECORE7",
                .desc = "Percentage of time in which Sampler pipeline active",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext6__sampler_busy_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext6_SAMPLER_BUSY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext7_SAMPLER_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext7_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext7";
    metric_set->symbol_name = "Ext7";
    metric_set->hw_config_guid = "714e9d80-e4e3-40e6-9e79-2ca6d1d0a5a5";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext7_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext7__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext7__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext7__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext7__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER L3 HIT L3BANK0",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK0",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK1",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK1",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK2",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK2",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK3",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK3",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK4",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK4",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK5",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK5",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK6",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK6",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 HIT L3BANK7",
                .symbol_name = "SAMPLER_L3_HIT_L3BANK7",
                .desc = "Number of L3 hit requests resulting from Sampler local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK0",
                .symbol_name = "SAMPLER_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK0_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK1",
                .symbol_name = "SAMPLER_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK1_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK2",
                .symbol_name = "SAMPLER_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK2_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK3",
                .symbol_name = "SAMPLER_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK3_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK4",
                .symbol_name = "SAMPLER_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK4_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK5",
                .symbol_name = "SAMPLER_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK5_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK6",
                .symbol_name = "SAMPLER_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK6_availability,
            },

            {
                .name = "SAMPLER L3 READ L3BANK7",
                .symbol_name = "SAMPLER_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests resulting from Sampler local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext7__sampler_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext7_SAMPLER_L3_READ_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext8_ICACHE_L3_READ_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext8_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext8";
    metric_set->symbol_name = "Ext8";
    metric_set->hw_config_guid = "30499dfb-3977-4808-a34c-93e7b50e0454";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext8_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext8__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext8__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext8__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext8__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE L3 HIT L3BANK0",
                .symbol_name = "ICACHE_L3_HIT_L3BANK0",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK1",
                .symbol_name = "ICACHE_L3_HIT_L3BANK1",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK2",
                .symbol_name = "ICACHE_L3_HIT_L3BANK2",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK3",
                .symbol_name = "ICACHE_L3_HIT_L3BANK3",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK4",
                .symbol_name = "ICACHE_L3_HIT_L3BANK4",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK5",
                .symbol_name = "ICACHE_L3_HIT_L3BANK5",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK6",
                .symbol_name = "ICACHE_L3_HIT_L3BANK6",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 HIT L3BANK7",
                .symbol_name = "ICACHE_L3_HIT_L3BANK7",
                .desc = "Number of XVE instruction cache requests that hit the L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK0",
                .symbol_name = "ICACHE_L3_READ_L3BANK0",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK0_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK1",
                .symbol_name = "ICACHE_L3_READ_L3BANK1",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK1_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK2",
                .symbol_name = "ICACHE_L3_READ_L3BANK2",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK2_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK3",
                .symbol_name = "ICACHE_L3_READ_L3BANK3",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK3_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK4",
                .symbol_name = "ICACHE_L3_READ_L3BANK4",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK4_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK5",
                .symbol_name = "ICACHE_L3_READ_L3BANK5",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK5_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK6",
                .symbol_name = "ICACHE_L3_READ_L3BANK6",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK6_availability,
            },

            {
                .name = "ICACHE L3 READ L3BANK7",
                .symbol_name = "ICACHE_L3_READ_L3BANK7",
                .desc = "Number of L3 read requests coming from XVE Instruction Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext8__icache_l3_read_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext8_ICACHE_L3_READ_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext9_Z_L3_ACCESS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext9_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext9";
    metric_set->symbol_name = "Ext9";
    metric_set->hw_config_guid = "417618f2-7a87-4745-bccd-6ba14d17bfa4";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext9_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext9__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext9__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext9__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext9__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "Z L3 ACCESS L3BANK0",
                .symbol_name = "Z_L3_ACCESS_L3BANK0",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK0_availability,
            },

            {
                .name = "Z L3 ACCESS L3BANK1",
                .symbol_name = "Z_L3_ACCESS_L3BANK1",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK1_availability,
            },

            {
                .name = "Z L3 ACCESS L3BANK2",
                .symbol_name = "Z_L3_ACCESS_L3BANK2",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK2_availability,
            },

            {
                .name = "Z L3 ACCESS L3BANK3",
                .symbol_name = "Z_L3_ACCESS_L3BANK3",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK3_availability,
            },

            {
                .name = "Z L3 ACCESS L3BANK4",
                .symbol_name = "Z_L3_ACCESS_L3BANK4",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK4_availability,
            },

            {
                .name = "Z L3 ACCESS L3BANK5",
                .symbol_name = "Z_L3_ACCESS_L3BANK5",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK5_availability,
            },

            {
                .name = "Z L3 ACCESS L3BANK6",
                .symbol_name = "Z_L3_ACCESS_L3BANK6",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK6_availability,
            },

            {
                .name = "Z L3 ACCESS L3BANK7",
                .symbol_name = "Z_L3_ACCESS_L3BANK7",
                .desc = "Number of L3 read requests resulting from Z local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext9__z_l3_access_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext9_Z_L3_ACCESS_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_COLOR_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext10_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext10";
    metric_set->symbol_name = "Ext10";
    metric_set->hw_config_guid = "443c32c7-e5e4-43da-b4f2-77efe45a60ed";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext10_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext10__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext10__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR L3 HIT L3BANK0",
                .symbol_name = "COLOR_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK1",
                .symbol_name = "COLOR_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK2",
                .symbol_name = "COLOR_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK3",
                .symbol_name = "COLOR_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK4",
                .symbol_name = "COLOR_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK5",
                .symbol_name = "COLOR_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK6",
                .symbol_name = "COLOR_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "COLOR L3 HIT L3BANK7",
                .symbol_name = "COLOR_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from color local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__color_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_COLOR_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK0",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK0",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK1",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK1",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK2",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK2",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK3",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK3",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK4",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK4",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK5",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK5",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK6",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK6",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "DATAPORT L3 HIT L3BANK7",
                .symbol_name = "DATAPORT_L3_HIT_L3BANK7",
                .desc = "Number of L3 hits for requests coming from the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext10__dataport_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext10_DATAPORT_L3_HIT_L3BANK7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext10__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext10__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext11_Z_L3_HIT_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext11_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext11";
    metric_set->symbol_name = "Ext11";
    metric_set->hw_config_guid = "3833e442-880a-4746-9df1-6347b7e5a081";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext11_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext11__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext11__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext11__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext11__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK0",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK0",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK0_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK1",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK1",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK1_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK2",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK2",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK2_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK3",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK3",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK3_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK4",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK4",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK4_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK5",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK5",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK5_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK6",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK6",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK6_availability,
            },

            {
                .name = "L3 ATOMIC ACCESS L3BANK7",
                .symbol_name = "L3_ATOMIC_ACCESS_L3BANK7",
                .desc = "Number of atomic accesses to L3 Bank",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__l3_atomic_access_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_L3_ATOMIC_ACCESS_L3BANK7_availability,
            },

            {
                .name = "Z L3 HIT L3BANK0",
                .symbol_name = "Z_L3_HIT_L3BANK0",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK0_availability,
            },

            {
                .name = "Z L3 HIT L3BANK1",
                .symbol_name = "Z_L3_HIT_L3BANK1",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK1_availability,
            },

            {
                .name = "Z L3 HIT L3BANK2",
                .symbol_name = "Z_L3_HIT_L3BANK2",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK2_availability,
            },

            {
                .name = "Z L3 HIT L3BANK3",
                .symbol_name = "Z_L3_HIT_L3BANK3",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK3_availability,
            },

            {
                .name = "Z L3 HIT L3BANK4",
                .symbol_name = "Z_L3_HIT_L3BANK4",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK4_availability,
            },

            {
                .name = "Z L3 HIT L3BANK5",
                .symbol_name = "Z_L3_HIT_L3BANK5",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK5_availability,
            },

            {
                .name = "Z L3 HIT L3BANK6",
                .symbol_name = "Z_L3_HIT_L3BANK6",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK6_availability,
            },

            {
                .name = "Z L3 HIT L3BANK7",
                .symbol_name = "Z_L3_HIT_L3BANK7",
                .desc = "Number of L3 read requests resulting from Z local cache miss which hits in L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext11__z_l3_hit_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext11_Z_L3_HIT_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext12_L3_OUTPUT_READY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext12_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext12";
    metric_set->symbol_name = "Ext12";
    metric_set->hw_config_guid = "931bb082-6f87-450e-8910-fd6a4ab206f7";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext12_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext12__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext12__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext12__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext12__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK0",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK0",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK0_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK1",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK1",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK1_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK2",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK2",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK2_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK3",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK3",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK3_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK4",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK4",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK4_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK5",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK5",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK5_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK6",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK6",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK6_availability,
            },

            {
                .name = "L3 INPUT AVAILABLE L3BANK7",
                .symbol_name = "L3_INPUT_AVAILABLE_L3BANK7",
                .desc = "Percentage of time in which L3 Bank has input requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_input_available_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_INPUT_AVAILABLE_L3BANK7_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK0",
                .symbol_name = "L3_OUTPUT_READY_L3BANK0",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK0_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK1",
                .symbol_name = "L3_OUTPUT_READY_L3BANK1",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK1_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK2",
                .symbol_name = "L3_OUTPUT_READY_L3BANK2",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK2_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK3",
                .symbol_name = "L3_OUTPUT_READY_L3BANK3",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK3_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK4",
                .symbol_name = "L3_OUTPUT_READY_L3BANK4",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK4_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK5",
                .symbol_name = "L3_OUTPUT_READY_L3BANK5",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK5_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK6",
                .symbol_name = "L3_OUTPUT_READY_L3BANK6",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK6_availability,
            },

            {
                .name = "L3 OUTPUT READY L3BANK7",
                .symbol_name = "L3_OUTPUT_READY_L3BANK7",
                .desc = "Percentage of time in which L3 Bank has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext12__l3_output_ready_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext12_L3_OUTPUT_READY_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext13_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext13";
    metric_set->symbol_name = "Ext13";
    metric_set->hw_config_guid = "f7fdd159-e273-47ab-99bc-f4fc410c6053";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext13_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext13__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext13__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR L3 ACCESS L3BANK0",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK0",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext13__color_l3_access_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK0_availability,
            },

            {
                .name = "COLOR L3 ACCESS L3BANK1",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK1",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext13__color_l3_access_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK1_availability,
            },

            {
                .name = "COLOR L3 ACCESS L3BANK2",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK2",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext13__color_l3_access_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK2_availability,
            },

            {
                .name = "COLOR L3 ACCESS L3BANK3",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK3",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext13__color_l3_access_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_COLOR_L3_ACCESS_L3BANK3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext13__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext13__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK0",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK0",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext13__l3_superq_full_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK0_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK1",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK1",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext13__l3_superq_full_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK1_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK2",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK2",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext13__l3_superq_full_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK2_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK3",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK3",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext13__l3_superq_full_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext13_L3_SUPERQ_FULL_L3BANK3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext14_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext14";
    metric_set->symbol_name = "Ext14";
    metric_set->hw_config_guid = "423732fb-f20a-4549-b632-53ac587668d9";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext14_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext14__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext14__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR L3 ACCESS L3BANK4",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK4",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext14__color_l3_access_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK4_availability,
            },

            {
                .name = "COLOR L3 ACCESS L3BANK5",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK5",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext14__color_l3_access_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK5_availability,
            },

            {
                .name = "COLOR L3 ACCESS L3BANK6",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK6",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext14__color_l3_access_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK6_availability,
            },

            {
                .name = "COLOR L3 ACCESS L3BANK7",
                .symbol_name = "COLOR_L3_ACCESS_L3BANK7",
                .desc = "Number of L3 request resulting from color local cache miss",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext14__color_l3_access_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_COLOR_L3_ACCESS_L3BANK7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext14__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext14__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 SUPERQ FULL L3BANK4",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK4",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext14__l3_superq_full_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK4_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK5",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK5",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext14__l3_superq_full_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK5_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK6",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK6",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext14__l3_superq_full_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK6_availability,
            },

            {
                .name = "L3 SUPERQ FULL L3BANK7",
                .symbol_name = "L3_SUPERQ_FULL_L3BANK7",
                .desc = "Percentage of time in which all slots in L3 request queue are waiting for data return / response",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext14__l3_superq_full_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext14_L3_SUPERQ_FULL_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext15_L3_BUSY_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext15_L3_BUSY_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext15_L3_BUSY_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext15_L3_BUSY_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext15_L3_STALL_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext15_L3_STALL_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext15_L3_STALL_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext15_L3_STALL_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext15_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext15";
    metric_set->symbol_name = "Ext15";
    metric_set->hw_config_guid = "0fa8f991-d412-4014-a7a7-be08ccf5fc4c";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext15_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext15__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext15__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext15__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext15__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BUSY L3BANK0",
                .symbol_name = "L3_BUSY_L3BANK0",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_busy_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_BUSY_L3BANK0_availability,
            },

            {
                .name = "L3 BUSY L3BANK1",
                .symbol_name = "L3_BUSY_L3BANK1",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_busy_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_BUSY_L3BANK1_availability,
            },

            {
                .name = "L3 BUSY L3BANK2",
                .symbol_name = "L3_BUSY_L3BANK2",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_busy_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_BUSY_L3BANK2_availability,
            },

            {
                .name = "L3 BUSY L3BANK3",
                .symbol_name = "L3_BUSY_L3BANK3",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_busy_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_BUSY_L3BANK3_availability,
            },

            {
                .name = "L3 STALL L3BANK0",
                .symbol_name = "L3_STALL_L3BANK0",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_stall_l3_bank0__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_STALL_L3BANK0_availability,
            },

            {
                .name = "L3 STALL L3BANK1",
                .symbol_name = "L3_STALL_L3BANK1",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_stall_l3_bank1__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_STALL_L3BANK1_availability,
            },

            {
                .name = "L3 STALL L3BANK2",
                .symbol_name = "L3_STALL_L3BANK2",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_stall_l3_bank2__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_STALL_L3BANK2_availability,
            },

            {
                .name = "L3 STALL L3BANK3",
                .symbol_name = "L3_STALL_L3BANK3",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext15__l3_stall_l3_bank3__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext15_L3_STALL_L3BANK3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext16_L3_BUSY_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext16_L3_BUSY_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext16_L3_BUSY_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext16_L3_BUSY_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext16_L3_STALL_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext16_L3_STALL_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext16_L3_STALL_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext16_L3_STALL_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext16_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext16";
    metric_set->symbol_name = "Ext16";
    metric_set->hw_config_guid = "e37de2da-c16f-4b2a-82bc-e1062fabfa2a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext16_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext16__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext16__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext16__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext16__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 BUSY L3BANK4",
                .symbol_name = "L3_BUSY_L3BANK4",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_busy_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_BUSY_L3BANK4_availability,
            },

            {
                .name = "L3 BUSY L3BANK5",
                .symbol_name = "L3_BUSY_L3BANK5",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_busy_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_BUSY_L3BANK5_availability,
            },

            {
                .name = "L3 BUSY L3BANK6",
                .symbol_name = "L3_BUSY_L3BANK6",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_busy_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_BUSY_L3BANK6_availability,
            },

            {
                .name = "L3 BUSY L3BANK7",
                .symbol_name = "L3_BUSY_L3BANK7",
                .desc = "Percentage of time in which L3 request queue has one or more requests pending",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_busy_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_BUSY_L3BANK7_availability,
            },

            {
                .name = "L3 STALL L3BANK4",
                .symbol_name = "L3_STALL_L3BANK4",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_stall_l3_bank4__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_STALL_L3BANK4_availability,
            },

            {
                .name = "L3 STALL L3BANK5",
                .symbol_name = "L3_STALL_L3BANK5",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_stall_l3_bank5__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_STALL_L3BANK5_availability,
            },

            {
                .name = "L3 STALL L3BANK6",
                .symbol_name = "L3_STALL_L3BANK6",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_stall_l3_bank6__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_STALL_L3BANK6_availability,
            },

            {
                .name = "L3 STALL L3BANK7",
                .symbol_name = "L3_STALL_L3BANK7",
                .desc = "Percentage of time in which L3 Bank Stalled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext16__l3_stall_l3_bank7__read,
                .max_float = percentage_max_callback_float,
                .group = "GTI/L3",
                .availability = mtlgt3_ext16_L3_STALL_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext17_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext17";
    metric_set->symbol_name = "Ext17";
    metric_set->hw_config_guid = "e8a60701-f694-496d-95be-34cc80796a46";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext17_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext17__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext17__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext17__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext17__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext17__load_store_cache_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext17_LOAD_STORE_CACHE_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext18_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext18";
    metric_set->symbol_name = "Ext18";
    metric_set->hw_config_guid = "1c957158-09ff-4a89-aa5b-3c1b4e46f9ba";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext18_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext18__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext18__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext18__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext18__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE INPUT AVAILABLE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has input available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE OUTPUT READY XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Load Store Cache has output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext18__load_store_cache_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext18_LOAD_STORE_CACHE_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext21_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext21";
    metric_set->symbol_name = "Ext21";
    metric_set->hw_config_guid = "a0b46166-6078-4045-8321-6df39b8e8ced";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext21_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext21__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext21__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext21__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext21__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE0",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_l3_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE1",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_l3_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE2",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_l3_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE3",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext21__load_store_cache_l3_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext21_LOAD_STORE_CACHE_L3_READ_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext22_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext22";
    metric_set->symbol_name = "Ext22";
    metric_set->hw_config_guid = "92371114-aa03-46d8-ab34-6e843fc92123";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext22_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext22__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext22__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext22__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext22__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE ACCESS XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Load Store Cache accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE4",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_l3_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE5",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_l3_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE6",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_l3_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 READ XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_READ_XECORE7",
                .desc = "Number of cacheline read requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext22__load_store_cache_l3_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext22_LOAD_STORE_CACHE_L3_READ_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext23_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext23";
    metric_set->symbol_name = "Ext23";
    metric_set->hw_config_guid = "c7cd47a5-39e8-4c58-9b4f-a9c6df869db8";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext23_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext23__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext23__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext23__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext23__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE0",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext23__load_store_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE1",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext23__load_store_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE2",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext23__load_store_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE3",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext23__load_store_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext23_LOAD_STORE_CACHE_HIT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext24_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext24";
    metric_set->symbol_name = "Ext24";
    metric_set->hw_config_guid = "2adf2c05-e151-4fa7-9e77-2331bd94235e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext24_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext24__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext24__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext24__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext24__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE4",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext24__load_store_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE5",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext24__load_store_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE6",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext24__load_store_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE HIT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_HIT_XECORE7",
                .desc = "Number of Load Store Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext24__load_store_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext24_LOAD_STORE_CACHE_HIT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext28_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext28";
    metric_set->symbol_name = "Ext28";
    metric_set->hw_config_guid = "1fcdcf0a-54da-4397-8832-c884d8d0b3ff";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext28_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext28__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext28__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext28__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext28__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE0",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_l3_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE1",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_l3_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE2",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_l3_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE3",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_l3_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_L3_WRITE_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_partial_write_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_partial_write_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_partial_write_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext28__load_store_cache_partial_write_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext28_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext29_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext29";
    metric_set->symbol_name = "Ext29";
    metric_set->hw_config_guid = "9701aca8-76a6-49ee-96c9-ff983f24d29e";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext29_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext29__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext29__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext29__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext29__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE4",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_l3_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE5",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_l3_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE6",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_l3_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE L3 WRITE XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_L3_WRITE_XECORE7",
                .desc = "Number of cacheline write requests from the Load Store Cache to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_l3_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_L3_WRITE_XECORE7_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_partial_write_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_partial_write_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_partial_write_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE PARTIAL WRITE COUNT XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7",
                .desc = "Number of writes to the Load Store Cache that don't fill a subsector",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext29__load_store_cache_partial_write_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext29_LOAD_STORE_CACHE_PARTIAL_WRITE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext31_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext31";
    metric_set->symbol_name = "Ext31";
    metric_set->hw_config_guid = "f47e74cf-7966-43ea-bbac-46f9a0d1dc1f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext31_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext31__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext31__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext31__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext31__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext31__xve_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext31_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext32_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext32";
    metric_set->symbol_name = "Ext32";
    metric_set->hw_config_guid = "3e220edc-390e-4964-9e57-4d45f3e01de8";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext32_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext32__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext32__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext32__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext32__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext32__xve_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext32_XVE_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext35_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext35";
    metric_set->symbol_name = "Ext35";
    metric_set->hw_config_guid = "d334294d-8dd2-4ae2-ae31-7d0d4acc2b6b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext35_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext35__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext35__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext35__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext35__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext35__xve_load_store_cache_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext35_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext36_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext36";
    metric_set->symbol_name = "Ext36";
    metric_set->hw_config_guid = "b749495f-4fc4-4e54-965e-38990758473b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext36_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext36__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext36__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext36__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext36__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext36__xve_load_store_cache_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext36_XVE_LOAD_STORE_CACHE_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext39_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext39";
    metric_set->symbol_name = "Ext39";
    metric_set->hw_config_guid = "09c0f842-3711-48f5-bf3e-74c1caa9f791";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext39_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext39__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext39__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext39__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext39__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext39__xve_load_store_cache_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext39_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext40_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext40";
    metric_set->symbol_name = "Ext40";
    metric_set->hw_config_guid = "be7c864e-0538-420d-916d-ce3aed7742ba";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext40_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext40__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext40__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext40__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext40__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext40__xve_load_store_cache_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext40_XVE_LOAD_STORE_CACHE_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext43_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext43_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext43_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext43_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext43_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext43";
    metric_set->symbol_name = "Ext43";
    metric_set->hw_config_guid = "86cf3d13-947b-4f7f-9685-1ff59ec342dd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext43_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext43__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext43__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext43__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext43__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext43__xve_load_store_cache_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext43_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext43__xve_load_store_cache_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext43_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext43__xve_load_store_cache_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext43_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext43__xve_load_store_cache_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext43_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext44_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext44_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext44_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext44_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext44_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext44";
    metric_set->symbol_name = "Ext44";
    metric_set->hw_config_guid = "7675136e-a91e-4bf8-b206-32591b878339";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext44_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext44__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext44__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext44__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext44__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext44__xve_load_store_cache_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext44_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext44__xve_load_store_cache_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext44_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext44__xve_load_store_cache_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext44_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext44__xve_load_store_cache_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext44_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext45_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext45_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext45_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext45_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext45_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext45";
    metric_set->symbol_name = "Ext45";
    metric_set->hw_config_guid = "e953dbdb-3451-4912-80ae-241ecc56a59e";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext45_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext45__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext45__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext45__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext45__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext45__xve_load_store_cache_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext45_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext45__xve_load_store_cache_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext45_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext45__xve_load_store_cache_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext45_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext45__xve_load_store_cache_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext45_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext46_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext46_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext46_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext46_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext46_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext46";
    metric_set->symbol_name = "Ext46";
    metric_set->hw_config_guid = "94219d74-6a23-4b93-bf62-88c9ad4ed4bd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext46_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext46__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext46__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext46__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext46__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext46__xve_load_store_cache_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext46_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic operations sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext46__xve_load_store_cache_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext46_XVE_LOAD_STORE_CACHE_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext46__xve_load_store_cache_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext46_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent by XVEs to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext46__xve_load_store_cache_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext46_XVE_LOAD_STORE_CACHE_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext51_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext51";
    metric_set->symbol_name = "Ext51";
    metric_set->hw_config_guid = "cab52f96-c6bf-48ca-a34e-17e52cadc8a6";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext51_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext51__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext51__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext51__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext51__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE LOAD STORE CACHE REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from the Load Store Cache back to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext51__xve_load_store_cache_register_response_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext51_XVE_LOAD_STORE_CACHE_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext53_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext53";
    metric_set->symbol_name = "Ext53";
    metric_set->hw_config_guid = "e4597eb9-ffa4-4da5-a180-5e12299f22cc";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext53_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext53__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext53__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext53__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext53__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext53__xve_slm_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext53__xve_slm_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext53__xve_slm_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext53__xve_slm_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext53_XVE_SLM_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext54_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext54";
    metric_set->symbol_name = "Ext54";
    metric_set->hw_config_guid = "0a11c113-298b-4f77-a085-1b7cac225015";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext54_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext54__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext54__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext54__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext54__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext54__xve_slm_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext54__xve_slm_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext54__xve_slm_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM read messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext54__xve_slm_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext54_XVE_SLM_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext57_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext57";
    metric_set->symbol_name = "Ext57";
    metric_set->hw_config_guid = "6f983509-03f1-463a-be88-3e4a40de40b4";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext57_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext57__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext57__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext57__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext57__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext57__xve_slm_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext57__xve_slm_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext57__xve_slm_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext57__xve_slm_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext57_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext58_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext58";
    metric_set->symbol_name = "Ext58";
    metric_set->hw_config_guid = "75d3fdde-e74d-4ec2-a7f0-f88fe5971af3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext58_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext58__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext58__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext58__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext58__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext58__xve_slm_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext58__xve_slm_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext58__xve_slm_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM write messages sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext58__xve_slm_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext58_XVE_SLM_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext61_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext61";
    metric_set->symbol_name = "Ext61";
    metric_set->hw_config_guid = "98c25532-687f-489a-b070-667edd3c41f9";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext61_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext61__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext61__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext61__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext61__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext61__xve_slm_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext61__xve_slm_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext61__xve_slm_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext61__xve_slm_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext61_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext62_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext62";
    metric_set->symbol_name = "Ext62";
    metric_set->hw_config_guid = "6ee28b50-5390-4655-af96-9d99569aee82";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext62_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext62__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext62__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext62__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext62__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext62__xve_slm_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext62__xve_slm_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext62__xve_slm_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM fence operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext62__xve_slm_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext62_XVE_SLM_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext65_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext65";
    metric_set->symbol_name = "Ext65";
    metric_set->hw_config_guid = "89a4a65b-cbfa-4c75-99fb-e5d7f0def495";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext65_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext65__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext65__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext65__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext65__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext65__xve_slm_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext65__xve_slm_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext65_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext66_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext66";
    metric_set->symbol_name = "Ext66";
    metric_set->hw_config_guid = "99e44f76-928f-4835-866f-663e25c69f66";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext66_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext66__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext66__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext66__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext66__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext66__xve_slm_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext66__xve_slm_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext66_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext67_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext67";
    metric_set->symbol_name = "Ext67";
    metric_set->hw_config_guid = "f45dfc0c-70ef-48bd-83a2-30cf4a6ba0d5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext67_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext67__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext67__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext67__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext67__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext67__xve_slm_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext67__xve_slm_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext67_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext68_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext68";
    metric_set->symbol_name = "Ext68";
    metric_set->hw_config_guid = "eab0942c-5181-4caf-aeec-44d9a0b69ada";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext68_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext68__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext68__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext68__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext68__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext68__xve_slm_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE SLM ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of SLM atomic operations sent by XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext68__xve_slm_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext68_XVE_SLM_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext73_DATAPORT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext73_DATAPORT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext73_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext73";
    metric_set->symbol_name = "Ext73";
    metric_set->hw_config_guid = "d9d0c398-6429-4ba8-bc08-6e8556a5880f";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext73_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext73__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext73__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE0",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext73__dataport_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext73_DATAPORT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE1",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext73__dataport_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext73_DATAPORT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext73__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext73__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext74_DATAPORT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext74_DATAPORT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext74_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext74";
    metric_set->symbol_name = "Ext74";
    metric_set->hw_config_guid = "d91bf24f-08af-4d1d-b957-c2293923c9a4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext74_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext74__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext74__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE2",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext74__dataport_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext74_DATAPORT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE3",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext74__dataport_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext74_DATAPORT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext74__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext74__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext75_DATAPORT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext75_DATAPORT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext75_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext75";
    metric_set->symbol_name = "Ext75";
    metric_set->hw_config_guid = "b5c2eaef-cffa-490b-a80e-de2b37ca63d8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext75_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext75__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext75__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE4",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext75__dataport_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext75_DATAPORT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE5",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext75__dataport_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext75_DATAPORT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext75__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext75__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext76_DATAPORT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext76_DATAPORT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext76_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext76";
    metric_set->symbol_name = "Ext76";
    metric_set->hw_config_guid = "d5cdafcf-483d-40f7-8dc9-feca73e94246";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext76_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext76__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext76__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE6",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext76__dataport_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext76_DATAPORT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "DATAPORT INPUT AVAILABLE XECORE7",
                .symbol_name = "DATAPORT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which XVEs have requests to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext76__dataport_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext76_DATAPORT_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext76__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext76__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext77_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext77";
    metric_set->symbol_name = "Ext77";
    metric_set->hw_config_guid = "240802cf-de55-472f-9e0a-710270ae9487";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext77_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext77__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext77__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE0",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext77__dataport_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE1",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext77__dataport_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE2",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext77__dataport_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE3",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext77__dataport_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext77_DATAPORT_OUTPUT_READY_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext77__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext77__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext78_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext78";
    metric_set->symbol_name = "Ext78";
    metric_set->hw_config_guid = "3dd49211-aa69-4711-87c2-97289ff9cfff";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext78_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext78__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext78__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE4",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext78__dataport_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE5",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext78__dataport_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE6",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext78__dataport_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "DATAPORT OUTPUT READY XECORE7",
                .symbol_name = "DATAPORT_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which the Dataport has data to return to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext78__dataport_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext78_DATAPORT_OUTPUT_READY_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext78__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext78__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext79_DATAPORT_BYTE_READ_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext79_DATAPORT_BYTE_READ_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext79_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext79";
    metric_set->symbol_name = "Ext79";
    metric_set->hw_config_guid = "64aeba75-9dbe-4231-81f6-8c991b84c070";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext79_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext79__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext79__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE0",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE0",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext79__dataport_byte_read_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext79_DATAPORT_BYTE_READ_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE1",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE1",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext79__dataport_byte_read_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext79_DATAPORT_BYTE_READ_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext79__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext79__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext80_DATAPORT_BYTE_READ_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext80_DATAPORT_BYTE_READ_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext80_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext80";
    metric_set->symbol_name = "Ext80";
    metric_set->hw_config_guid = "3b293ce5-af38-4ae2-96f4-a542d3c68d5e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext80_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext80__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext80__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE2",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE2",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext80__dataport_byte_read_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext80_DATAPORT_BYTE_READ_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE3",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE3",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext80__dataport_byte_read_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext80_DATAPORT_BYTE_READ_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext80__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext80__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext81_DATAPORT_BYTE_READ_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext81_DATAPORT_BYTE_READ_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext81_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext81";
    metric_set->symbol_name = "Ext81";
    metric_set->hw_config_guid = "09516dce-66a0-499f-8457-97f78bb921e6";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext81_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext81__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext81__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE4",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE4",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext81__dataport_byte_read_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext81_DATAPORT_BYTE_READ_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE5",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE5",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext81__dataport_byte_read_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext81_DATAPORT_BYTE_READ_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext81__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext81__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext82_DATAPORT_BYTE_READ_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext82_DATAPORT_BYTE_READ_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext82_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext82";
    metric_set->symbol_name = "Ext82";
    metric_set->hw_config_guid = "c0bdc35b-af55-4ac9-8078-f22578201756";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext82_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext82__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext82__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE READ XECORE6",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE6",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext82__dataport_byte_read_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext82_DATAPORT_BYTE_READ_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE READ XECORE7",
                .symbol_name = "DATAPORT_BYTE_READ_XECORE7",
                .desc = "Number of bytes read through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext82__dataport_byte_read_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext82_DATAPORT_BYTE_READ_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext82__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext82__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext83_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext83";
    metric_set->symbol_name = "Ext83";
    metric_set->hw_config_guid = "7f4b6bdf-4a28-4e6b-a67b-c9a0d320ddb8";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext83_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext83__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext83__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE0",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE0",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE0_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE1",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE1",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE1_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE2",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE2",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE2_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE3",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE3",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE3_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE4",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE4",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE4_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE5",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE5",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE5_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE6",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE6",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE6_availability,
            },

            {
                .name = "DATAPORT BYTE WRITE XECORE7",
                .symbol_name = "DATAPORT_BYTE_WRITE_XECORE7",
                .desc = "Number of bytes written through the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext83__dataport_byte_write_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_BYTE_WRITE_XECORE7_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of cacheline requests from the Dataport to the Render Cache not including uncached accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext83__dataport_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext83_DATAPORT_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext83__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext83__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext85_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext85";
    metric_set->symbol_name = "Ext85";
    metric_set->hw_config_guid = "e19c5430-c632-43eb-b27f-eeb3d405bfd8";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext85_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext85__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext85__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE0",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE0",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__dataport_texture_cache_hit_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE0_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE1",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE1",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__dataport_texture_cache_hit_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE1_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE2",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE2",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__dataport_texture_cache_hit_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE2_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE3",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE3",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__dataport_texture_cache_hit_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_DATAPORT_TEXTURE_CACHE_HIT_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext85__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext85__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__xve_dataport_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__xve_dataport_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__xve_dataport_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext85__xve_dataport_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext85_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext86_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext86";
    metric_set->symbol_name = "Ext86";
    metric_set->hw_config_guid = "d379e5f5-32f3-4a6b-957f-5ccf607dda00";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext86_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext86__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext86__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE4",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE4",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__dataport_texture_cache_hit_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE4_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE5",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE5",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__dataport_texture_cache_hit_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE5_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE6",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE6",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__dataport_texture_cache_hit_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE6_availability,
            },

            {
                .name = "DATAPORT TEXTURE CACHE HIT XECORE7",
                .symbol_name = "DATAPORT_TEXTURE_CACHE_HIT_XECORE7",
                .desc = "Number of cache requests from the Dataport to the Render Cache that resulted in a cache hit",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__dataport_texture_cache_hit_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_DATAPORT_TEXTURE_CACHE_HIT_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext86__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext86__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__xve_dataport_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__xve_dataport_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__xve_dataport_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT READ MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext86__xve_dataport_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext86_XVE_DATAPORT_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext87_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext87";
    metric_set->symbol_name = "Ext87";
    metric_set->hw_config_guid = "3e86ea71-8695-4815-ac18-0fd4510541a1";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext87_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext87__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext87__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext87__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext87__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext87__xve_dataport_write_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext87__xve_dataport_write_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext87__xve_dataport_write_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext87__xve_dataport_write_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext87_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext88_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext88";
    metric_set->symbol_name = "Ext88";
    metric_set->hw_config_guid = "31ad28aa-7425-4bb4-b1a3-423821d98d84";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext88_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext88__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext88__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext88__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext88__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext88__xve_dataport_write_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext88__xve_dataport_write_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext88__xve_dataport_write_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT WRITE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext88__xve_dataport_write_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext88_XVE_DATAPORT_WRITE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext91_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext91";
    metric_set->symbol_name = "Ext91";
    metric_set->hw_config_guid = "a1963e82-2bad-44e2-9bb1-ee18657c09cd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext91_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext91__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext91__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext91__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext91__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext91__xve_dataport_atomic_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext91__xve_dataport_atomic_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext91__xve_dataport_atomic_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext91__xve_dataport_atomic_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext91_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext92_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext92";
    metric_set->symbol_name = "Ext92";
    metric_set->hw_config_guid = "fdf0722d-cb2e-46bd-8c1f-a85c6fbca3ff";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext92_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext92__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext92__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext92__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext92__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext92__xve_dataport_atomic_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext92__xve_dataport_atomic_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext92__xve_dataport_atomic_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT ATOMIC MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7",
                .desc = "Number of atomic messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext92__xve_dataport_atomic_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext92_XVE_DATAPORT_ATOMIC_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext93_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext93";
    metric_set->symbol_name = "Ext93";
    metric_set->hw_config_guid = "e0810ece-3bb5-4786-871b-b504faa00ba7";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext93_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext93__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext93__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext93__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext93__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext93__xve_dataport_register_response_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = mtlgt3__ext93__xve_dataport_register_response_count_xecore1__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext93_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext94_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext94";
    metric_set->symbol_name = "Ext94";
    metric_set->hw_config_guid = "8697d9f7-3085-4ae7-b88d-e77697972732";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext94_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext94__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext94__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext94__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext94__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = mtlgt3__ext94__xve_dataport_register_response_count_xecore2__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = mtlgt3__ext94__xve_dataport_register_response_count_xecore3__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext94_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext95_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext95";
    metric_set->symbol_name = "Ext95";
    metric_set->hw_config_guid = "d059b804-fc25-4cbc-9682-ebc806a0d423";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext95_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext95__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext95__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext95__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext95__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = mtlgt3__ext95__xve_dataport_register_response_count_xecore4__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = mtlgt3__ext95__xve_dataport_register_response_count_xecore5__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext95_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext96_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext96";
    metric_set->symbol_name = "Ext96";
    metric_set->hw_config_guid = "ca3c5e8c-b83a-474f-85fa-af7572a1ce27";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext96_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext96__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext96__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext96__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext96__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = mtlgt3__ext96__xve_dataport_register_response_count_xecore6__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER RESPONSE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7",
                .desc = "Number of return message payload transactions sent from the Dataport to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_float = mtlgt3__ext96__xve_dataport_register_response_count_xecore7__read,
                .max_float = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext96_XVE_DATAPORT_REGISTER_RESPONSE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext97_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext97";
    metric_set->symbol_name = "Ext97";
    metric_set->hw_config_guid = "fbed5532-2b4f-4194-b856-0404c387b2e4";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext97_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext97__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext97__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext97__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext97__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT REGISTER REQUEST COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7",
                .desc = "Number of message payload transactions sent from XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext97__xve_dataport_register_request_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext97_XVE_DATAPORT_REGISTER_REQUEST_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext98_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext98";
    metric_set->symbol_name = "Ext98";
    metric_set->hw_config_guid = "4c975484-c2f5-4f29-b8fa-8ec1068de77a";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext98_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext98__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext98__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext98__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext98__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE0",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE0",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext98__sampler_output_ready_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE0_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE1",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE1",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext98__sampler_output_ready_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE1_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE2",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE2",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext98__sampler_output_ready_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE2_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE3",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE3",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext98__sampler_output_ready_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext98_SAMPLER_OUTPUT_READY_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext99_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext99";
    metric_set->symbol_name = "Ext99";
    metric_set->hw_config_guid = "13017c9d-9d3a-41d1-8f9c-2eafdcbefab4";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext99_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext99__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext99__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext99__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext99__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE4",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE4",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext99__sampler_output_ready_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE4_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE5",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE5",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext99__sampler_output_ready_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE5_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE6",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE6",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext99__sampler_output_ready_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE6_availability,
            },

            {
                .name = "SAMPLER OUTPUT READY XECORE7",
                .symbol_name = "SAMPLER_OUTPUT_READY_XECORE7",
                .desc = "Percentage of time in which Sampler output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext99__sampler_output_ready_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext99_SAMPLER_OUTPUT_READY_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext100_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext100";
    metric_set->symbol_name = "Ext100";
    metric_set->hw_config_guid = "a7ef0e01-74c3-48c5-8d0f-00241111cf69";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext100_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext100__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext100__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext100__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext100__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE0",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE1",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE2",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE3",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE0",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE0",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_memory_latency_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE0_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE1",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE1",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_memory_latency_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE1_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE2",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE2",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_memory_latency_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE2_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE3",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE3",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext100__sampler_memory_latency_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext100_SAMPLER_MEMORY_LATENCY_STALL_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext101_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext101";
    metric_set->symbol_name = "Ext101";
    metric_set->hw_config_guid = "7e86b43f-715e-419a-83eb-e8777fd7c77a";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext101_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext101__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext101__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext101__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext101__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE4",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE5",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE6",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "SAMPLER INPUT AVAILABLE XECORE7",
                .symbol_name = "SAMPLER_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Sampler input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE4",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE4",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_memory_latency_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE4_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE5",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE5",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_memory_latency_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE5_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE6",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE6",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_memory_latency_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE6_availability,
            },

            {
                .name = "SAMPLER MEMORY LATENCY STALL XECORE7",
                .symbol_name = "SAMPLER_MEMORY_LATENCY_STALL_XECORE7",
                .desc = "Percentage of time in which Sampler stalled due to latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext101__sampler_memory_latency_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext101_SAMPLER_MEMORY_LATENCY_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext102_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext102";
    metric_set->symbol_name = "Ext102";
    metric_set->hw_config_guid = "1fb36f5f-04a3-412f-a6ca-80233bf408a0";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext102_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext102__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext102__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext102__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext102__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE0",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE1",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE2",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE3",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE4",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE5",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE6",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH INPUT AVAILABLE XECORE7",
                .symbol_name = "THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE0",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE1",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE2",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE3",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE4",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE5",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE6",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH STALL XECORE7",
                .symbol_name = "THREAD_DISPATCH_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Dispatch is stalled waiting for threads to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext102__thread_dispatch_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext102_THREAD_DISPATCH_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext103_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext103";
    metric_set->symbol_name = "Ext103";
    metric_set->hw_config_guid = "5228137b-8e8d-4d67-b195-d5f64a88f5f0";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext103_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext103__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext103__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext103__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext103__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE ACCESS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7",
                .desc = "Number of Sampler L1 requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_access_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_ACCESS_XECORE7_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE0",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE0",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE1",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE1",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE2",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE2",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE3",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE3",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE3_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE4",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE4",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE5",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE5",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE6",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE6",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "SAMPLER TEXTURE CACHE MISS XECORE7",
                .symbol_name = "SAMPLER_TEXTURE_CACHE_MISS_XECORE7",
                .desc = "Number of Sampler L1 misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext103__sampler_texture_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext103_SAMPLER_TEXTURE_CACHE_MISS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext104_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext104_GPGPU_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext104_TASK_THREADGROUP_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext104_TASK_THREAD_EXIT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext104_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext104";
    metric_set->symbol_name = "Ext104";
    metric_set->hw_config_guid = "5503160a-7b2a-4099-9ec6-0d3a551cb388";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext104_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE0",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext104__async_gpgpu_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext104_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext104__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext104__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE2",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext104__gpgpu_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext104_GPGPU_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext104__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext104__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE2",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE2",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext104__task_threadgroup_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext104_TASK_THREADGROUP_COUNT_XECORE2_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE0",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE0",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext104__task_thread_exit_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext104_TASK_THREAD_EXIT_COUNT_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext105_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext105_GPGPU_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext105_TASK_THREADGROUP_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext105_TASK_THREAD_EXIT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext105_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext105";
    metric_set->symbol_name = "Ext105";
    metric_set->hw_config_guid = "418f87f0-b6d8-4684-883e-4f10a79c5070";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext105_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE1",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext105__async_gpgpu_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext105_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext105__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext105__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE3",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext105__gpgpu_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext105_GPGPU_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext105__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext105__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE3",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE3",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext105__task_threadgroup_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext105_TASK_THREADGROUP_COUNT_XECORE3_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE1",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE1",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext105__task_thread_exit_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext105_TASK_THREAD_EXIT_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext106_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext106_GPGPU_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext106_TASK_THREADGROUP_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext106_TASK_THREAD_EXIT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext106_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext106";
    metric_set->symbol_name = "Ext106";
    metric_set->hw_config_guid = "f5b7256f-9bf6-4c95-94c1-4044cfad0ea6";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext106_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE2",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext106__async_gpgpu_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext106_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE2_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext106__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext106__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE0",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext106__gpgpu_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext106_GPGPU_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext106__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext106__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE0",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE0",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext106__task_threadgroup_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext106_TASK_THREADGROUP_COUNT_XECORE0_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE2",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE2",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext106__task_thread_exit_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext106_TASK_THREAD_EXIT_COUNT_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext107_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext107_GPGPU_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext107_TASK_THREADGROUP_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext107_TASK_THREAD_EXIT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext107_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext107";
    metric_set->symbol_name = "Ext107";
    metric_set->hw_config_guid = "28d75db6-0eb3-4651-b820-513a76013504";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext107_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE3",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext107__async_gpgpu_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext107_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE3_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext107__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext107__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE1",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext107__gpgpu_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext107_GPGPU_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext107__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext107__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE1",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE1",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext107__task_threadgroup_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext107_TASK_THREADGROUP_COUNT_XECORE1_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE3",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE3",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext107__task_thread_exit_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext107_TASK_THREAD_EXIT_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext108_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext108_GPGPU_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext108_TASK_THREADGROUP_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext108_TASK_THREAD_EXIT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext108_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext108";
    metric_set->symbol_name = "Ext108";
    metric_set->hw_config_guid = "080da0b6-29a4-416b-b20f-ece0e2527f60";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext108_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE4",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext108__async_gpgpu_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext108_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE4_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext108__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext108__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE6",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext108__gpgpu_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext108_GPGPU_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext108__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext108__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE6",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE6",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext108__task_threadgroup_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext108_TASK_THREADGROUP_COUNT_XECORE6_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE4",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE4",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext108__task_thread_exit_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext108_TASK_THREAD_EXIT_COUNT_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext109_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext109_GPGPU_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext109_TASK_THREADGROUP_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext109_TASK_THREAD_EXIT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext109_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext109";
    metric_set->symbol_name = "Ext109";
    metric_set->hw_config_guid = "75a9e66d-9bbe-46d7-971e-71ca8ef680ff";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext109_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE5",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext109__async_gpgpu_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext109_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE5_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext109__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext109__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE7",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext109__gpgpu_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext109_GPGPU_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext109__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext109__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE7",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE7",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext109__task_threadgroup_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext109_TASK_THREADGROUP_COUNT_XECORE7_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE5",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE5",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext109__task_thread_exit_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext109_TASK_THREAD_EXIT_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext110_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext110_GPGPU_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext110_TASK_THREADGROUP_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext110_TASK_THREAD_EXIT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext110_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext110";
    metric_set->symbol_name = "Ext110";
    metric_set->hw_config_guid = "ae5589a9-7e09-4343-a611-3161977315d5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext110_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE6",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext110__async_gpgpu_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext110_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE6_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext110__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext110__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE4",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext110__gpgpu_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext110_GPGPU_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext110__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext110__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE4",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE4",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext110__task_threadgroup_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext110_TASK_THREADGROUP_COUNT_XECORE4_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE6",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE6",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext110__task_thread_exit_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext110_TASK_THREAD_EXIT_COUNT_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext111_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext111_GPGPU_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext111_TASK_THREADGROUP_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext111_TASK_THREAD_EXIT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext111_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext111";
    metric_set->symbol_name = "Ext111";
    metric_set->hw_config_guid = "a5e1e738-1338-4d76-a6a7-5517111cc852";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext111_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "ASYNC GPGPU THREAD EXIT COUNT XECORE7",
                .symbol_name = "ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Async GPGPU EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext111__async_gpgpu_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext111_ASYNC_GPGPU_THREAD_EXIT_COUNT_XECORE7_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext111__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext111__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU THREADGROUP COUNT XECORE5",
                .symbol_name = "GPGPU_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of GPGPU threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext111__gpgpu_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext111_GPGPU_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext111__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext111__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "TASK THREADGROUP COUNT XECORE5",
                .symbol_name = "TASK_THREADGROUP_COUNT_XECORE5",
                .desc = "Number of Task Shader threadgroups dispatched",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext111__task_threadgroup_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext111_TASK_THREADGROUP_COUNT_XECORE5_availability,
            },

            {
                .name = "TASK THREAD EXIT COUNT XECORE7",
                .symbol_name = "TASK_THREAD_EXIT_COUNT_XECORE7",
                .desc = "Number of Task Shader EOT messages received",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext111__task_thread_exit_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext111_TASK_THREAD_EXIT_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext113_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext113";
    metric_set->symbol_name = "Ext113";
    metric_set->hw_config_guid = "1a24edc7-8187-43b6-86aa-fcf56c223893";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext113_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext113__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext113__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext113__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext113__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE0",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE0",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE1",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE1",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE2",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE2",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE3",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE3",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_ps_active_cycles_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue0_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue0_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue0_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue0_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE3_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE0",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue1_active_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE0_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE1",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue1_active_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE1_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE2",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue1_active_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE2_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE3",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext113__thread_dispatch_queue1_active_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext113_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

static bool mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext114_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext114";
    metric_set->symbol_name = "Ext114";
    metric_set->hw_config_guid = "32565d07-8ac7-41c3-89a3-66d0c1100616";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext114_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext114__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext114__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext114__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext114__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE4",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE4",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE5",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE5",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE6",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE6",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH PS ACTIVE CYCLES XECORE7",
                .symbol_name = "THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE7",
                .desc = "Percentage of time in which Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_ps_active_cycles_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_PS_ACTIVE_CYCLES_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue0_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue0_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue0_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE0 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7",
                .desc = "Percentage of time in which non-Pixel Shader threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue0_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE0_ACTIVE_XECORE7_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE4",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue1_active_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE4_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE5",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue1_active_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE5_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE6",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue1_active_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE6_availability,
            },

            {
                .name = "THREAD DISPATCH QUEUE1 ACTIVE XECORE7",
                .symbol_name = "THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7",
                .desc = "Percentage of time in which Async GPGPU threads are ready for dispatch in a particular Xe core",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext114__thread_dispatch_queue1_active_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext114_THREAD_DISPATCH_QUEUE1_ACTIVE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

static bool mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext116_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext116";
    metric_set->symbol_name = "Ext116";
    metric_set->hw_config_guid = "f725009a-c5e7-4418-9adf-ddb70cb2edde";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext116_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext116__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext116__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext116__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext116__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext116__threadgroup_dispatch_resource_stall_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext116_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext117_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext117";
    metric_set->symbol_name = "Ext117";
    metric_set->hw_config_guid = "f633497f-c116-461f-a0e9-bb3fdcef7683";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext117_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext117__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext117__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext117__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext117__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH RESOURCE STALL XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7",
                .desc = "Percentage of time in which Thread Spawner is stalled waiting for resources to be available (SLM, Barrier, BTD stack)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext117__threadgroup_dispatch_resource_stall_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext117_THREADGROUP_DISPATCH_RESOURCE_STALL_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext118_AMFS_CACHE_HIT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_AMFS_CACHE_MISS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_AMFS_STALL_ALL_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_AMFS_STALL_ANY_INPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_RENDER_CACHE_HIT_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_RENDER_CACHE_READ_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext118_RENDER_CACHE_WRITE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext118_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext118";
    metric_set->symbol_name = "Ext118";
    metric_set->hw_config_guid = "bae9e67e-4b5c-4fb9-b21d-21a6966bed46";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext118_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE0",
                .symbol_name = "AMFS_CACHE_HIT_SLICE0",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext118__amfs_cache_hit_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext118_AMFS_CACHE_HIT_SLICE0_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE0",
                .symbol_name = "AMFS_CACHE_MISS_SLICE0",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext118__amfs_cache_miss_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext118_AMFS_CACHE_MISS_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext118__amfs_stall_all_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext118_AMFS_STALL_ALL_INPUT_SLICE0_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE0",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE0",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext118__amfs_stall_any_input_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext118_AMFS_STALL_ANY_INPUT_SLICE0_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext118__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext118__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext118__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext118__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE0",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE0",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext118__render_cache_hit_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext118_RENDER_CACHE_HIT_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE INPUT AVAILABLE _L3NODE0",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE0",
                .desc = "Percentage of time when Render Cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext118__render_cache_input_available_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext118_RENDER_CACHE_INPUT_AVAILABLE_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE OUTPUT READY _L3NODE0",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE0",
                .desc = "Percentage of time when Render Cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext118__render_cache_output_ready_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext118_RENDER_CACHE_OUTPUT_READY_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE0",
                .symbol_name = "RENDER_CACHE_READ_L3NODE0",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext118__render_cache_read_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext118_RENDER_CACHE_READ_L3NODE0_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE0",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE0",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext118__render_cache_write_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext118_RENDER_CACHE_WRITE_L3NODE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool mtlgt3_ext119_AMFS_CACHE_HIT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_AMFS_CACHE_MISS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_AMFS_STALL_ALL_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_AMFS_STALL_ANY_INPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_RENDER_CACHE_HIT_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_RENDER_CACHE_READ_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext119_RENDER_CACHE_WRITE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext119_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext119";
    metric_set->symbol_name = "Ext119";
    metric_set->hw_config_guid = "95c08faf-813c-4b71-9062-09569c5ff432";
    metric_set->counters = calloc(12, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext119_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS CACHE HIT SLICE1",
                .symbol_name = "AMFS_CACHE_HIT_SLICE1",
                .desc = "Number of hits in the AMFS cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext119__amfs_cache_hit_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext119_AMFS_CACHE_HIT_SLICE1_availability,
            },

            {
                .name = "AMFS CACHE MISS SLICE1",
                .symbol_name = "AMFS_CACHE_MISS_SLICE1",
                .desc = "Number of cache misses in AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext119__amfs_cache_miss_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext119_AMFS_CACHE_MISS_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ALL INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ALL_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at both of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext119__amfs_stall_all_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext119_AMFS_STALL_ALL_INPUT_SLICE1_availability,
            },

            {
                .name = "AMFS STALL ANY INPUT SLICE1",
                .symbol_name = "AMFS_STALL_ANY_INPUT_SLICE1",
                .desc = "Percentage of time in which AMFS stalls at any of the color pipe inputs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext119__amfs_stall_any_input_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext119_AMFS_STALL_ANY_INPUT_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext119__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext119__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext119__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext119__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE HIT L3NODE1",
                .symbol_name = "RENDER_CACHE_HIT_L3NODE1",
                .desc = "Number of Render Cache hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext119__render_cache_hit_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext119_RENDER_CACHE_HIT_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE INPUT AVAILABLE _L3NODE1",
                .symbol_name = "RENDER_CACHE_INPUT_AVAILABLE_L3NODE1",
                .desc = "Percentage of time when Render Cache input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext119__render_cache_input_available_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext119_RENDER_CACHE_INPUT_AVAILABLE_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE OUTPUT READY _L3NODE1",
                .symbol_name = "RENDER_CACHE_OUTPUT_READY_L3NODE1",
                .desc = "Percentage of time when Render Cache output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext119__render_cache_output_ready_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext119_RENDER_CACHE_OUTPUT_READY_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE READ L3NODE1",
                .symbol_name = "RENDER_CACHE_READ_L3NODE1",
                .desc = "Number of Render Cache reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext119__render_cache_read_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext119_RENDER_CACHE_READ_L3NODE1_availability,
            },

            {
                .name = "RENDER CACHE WRITE L3NODE1",
                .symbol_name = "RENDER_CACHE_WRITE_L3NODE1",
                .desc = "Number of Render Cache writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext119__render_cache_write_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext119_RENDER_CACHE_WRITE_L3NODE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 12);
}

static bool mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext120_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext120";
    metric_set->symbol_name = "Ext120";
    metric_set->hw_config_guid = "045ee54e-4e02-4877-adb1-5bd14ba49100";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext120_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext120__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext120__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext120__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext120__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE0",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext120__pixel_post_process_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE1",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext120__pixel_post_process_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE2",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext120__pixel_post_process_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE3",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext120__pixel_post_process_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext120_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext121_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext121";
    metric_set->symbol_name = "Ext121";
    metric_set->hw_config_guid = "2e3894b5-2b6a-49c4-b2b6-0dde7375cb7b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext121_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext121__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext121__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext121__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext121__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE4",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext121__pixel_post_process_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE5",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext121__pixel_post_process_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE6",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext121__pixel_post_process_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE XECORE7",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext121__pixel_post_process_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext121_PIXEL_POST_PROCESS_INPUT_AVAILABLE_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext122_AMFS_4X4_SHADING_REQUEST_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_AMFS_4X4_SHADING_REQUEST_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext122_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext122";
    metric_set->symbol_name = "Ext122";
    metric_set->hw_config_guid = "25ca1237-2ed3-447a-9767-1a85da89daef";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext122_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE0",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE0",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext122__amfs_4_x4_shading_request_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext122_AMFS_4X4_SHADING_REQUEST_SLICE0_availability,
            },

            {
                .name = "AMFS 4X4 SHADING REQUEST SLICE1",
                .symbol_name = "AMFS_4X4_SHADING_REQUEST_SLICE1",
                .desc = "Number of Shading Request (evaluate) messages processed by AMFS",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext122__amfs_4_x4_shading_request_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext122_AMFS_4X4_SHADING_REQUEST_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext122__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext122__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE1_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE2",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE2_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY1 STALL CPIPE3",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline stalled due to MultiSampling Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__color_pipe_cache_latency1_stall_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_COLOR_PIPE_CACHE_LATENCY1_STALL_CPIPE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext122__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext122__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__pixel_post_process_output_ready_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__pixel_post_process_output_ready_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE1_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__pixel_post_process_output_ready_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS OUTPUT READY CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline pixel output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext122__pixel_post_process_output_ready_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext122_PIXEL_POST_PROCESS_OUTPUT_READY_CPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}

static bool mtlgt3_ext123_AMFS_L3_ACCESS_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_AMFS_L3_ACCESS_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_AMFS_L3_ATOMIC_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_AMFS_L3_ATOMIC_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_PIXEL_BACKEND_OUTPUT_READY_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext123_PIXEL_BACKEND_OUTPUT_READY_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext123_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext123";
    metric_set->symbol_name = "Ext123";
    metric_set->hw_config_guid = "cf41fd07-c4c2-466c-9d85-774dcde02359";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext123_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 ACCESS SLICE0",
                .symbol_name = "AMFS_L3_ACCESS_SLICE0",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext123__amfs_l3_access_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext123_AMFS_L3_ACCESS_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ACCESS SLICE1",
                .symbol_name = "AMFS_L3_ACCESS_SLICE1",
                .desc = "Number of AMFS accesses to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext123__amfs_l3_access_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext123_AMFS_L3_ACCESS_SLICE1_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE0",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE0",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext123__amfs_l3_atomic_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext123_AMFS_L3_ATOMIC_SLICE0_availability,
            },

            {
                .name = "AMFS L3 ATOMIC SLICE1",
                .symbol_name = "AMFS_L3_ATOMIC_SLICE1",
                .desc = "Number of AMFS atomics to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext123__amfs_l3_atomic_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext123_AMFS_L3_ATOMIC_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext123__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext123__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext123__clipper_primitive_far_near_clip_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext123_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE FAR NEAR CLIP SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1",
                .desc = "Number of primitives clipped by Clipper due to near/far planes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext123__clipper_primitive_far_near_clip_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext123_CLIPPER_PRIMITIVE_FAR_NEAR_CLIP_SLICE1_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE0",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext123__color_pipe_cache_latency2_stall_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext123_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE0_availability,
            },

            {
                .name = "COLOR PIPE CACHE LATENCY2 STALL L3NODE1",
                .symbol_name = "COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1",
                .desc = "Percentage of time in which Color Pipeline stalled due to Render Cache latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext123__color_pipe_cache_latency2_stall_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext123_COLOR_PIPE_CACHE_LATENCY2_STALL_L3NODE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext123__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext123__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL BACKEND INPUT AVAILABLE _L3NODE0",
                .symbol_name = "PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE0",
                .desc = "Percentage of time when  the data is available at input of Pixel Backend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext123__pixel_backend_input_available_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext123_PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE0_availability,
            },

            {
                .name = "PIXEL BACKEND INPUT AVAILABLE _L3NODE1",
                .symbol_name = "PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE1",
                .desc = "Percentage of time when  the data is available at input of Pixel Backend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext123__pixel_backend_input_available_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext123_PIXEL_BACKEND_INPUT_AVAILABLE_L3NODE1_availability,
            },

            {
                .name = "PIXEL BACKEND OUTPUT READY _L3NODE0",
                .symbol_name = "PIXEL_BACKEND_OUTPUT_READY_L3NODE0",
                .desc = "Percentage of time when  the data at Pixel Backend output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext123__pixel_backend_output_ready_l3_node0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext123_PIXEL_BACKEND_OUTPUT_READY_L3NODE0_availability,
            },

            {
                .name = "PIXEL BACKEND OUTPUT READY _L3NODE1",
                .symbol_name = "PIXEL_BACKEND_OUTPUT_READY_L3NODE1",
                .desc = "Percentage of time when  the data at Pixel Backend output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext123__pixel_backend_output_ready_l3_node1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext123_PIXEL_BACKEND_OUTPUT_READY_L3NODE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

static bool mtlgt3_ext124_CLIPPER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_CLIPPER_INPUT_VERTEX_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_CLIPPER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_PS_OUTPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_PS_OUTPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_STRIPSFAN_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext124_VS_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext124_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext124";
    metric_set->symbol_name = "Ext124";
    metric_set->hw_config_guid = "2445e8f0-04c4-43f5-87ff-e2f99a2528ed";
    metric_set->counters = calloc(14, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext124_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext124__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext124__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE0",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__clipper_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_CLIPPER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE0",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE0",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext124__clipper_input_vertex_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext124_CLIPPER_INPUT_VERTEX_SLICE0_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE0",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__clipper_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_CLIPPER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE0",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext124__clipper_primitive_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext124_CLIPPER_PRIMITIVE_OUTPUT_SLICE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext124__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext124__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE0",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__ps_output_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_PS_OUTPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE1",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__ps_output_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_PS_OUTPUT_AVAILABLE_CPIPE1_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE0",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext124__streamout_output_vertex_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext124_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE0",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__stripsfan_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_STRIPSFAN_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE0",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__vertex_fetch_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_VERTEX_FETCH_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE0",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__vertex_fetch_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_VERTEX_FETCH_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE0",
                .symbol_name = "VS_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext124__vs_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext124_VS_OUTPUT_READY_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 14);
}

static bool mtlgt3_ext125_CLIPPER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_CLIPPER_INPUT_VERTEX_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_CLIPPER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_PS_OUTPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_PS_OUTPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_STRIPSFAN_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext125_VS_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext125_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext125";
    metric_set->symbol_name = "Ext125";
    metric_set->hw_config_guid = "446192f5-9062-4f1e-a99e-1be87cdcd0b8";
    metric_set->counters = calloc(14, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext125_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext125__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext125__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER INPUT AVAILABLE SLICE1",
                .symbol_name = "CLIPPER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Clipper has input available (from Vertex Shader or SOL)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__clipper_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_CLIPPER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "CLIPPER INPUT VERTEX SLICE1",
                .symbol_name = "CLIPPER_INPUT_VERTEX_SLICE1",
                .desc = "Number of Clipper input vertices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext125__clipper_input_vertex_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext125_CLIPPER_INPUT_VERTEX_SLICE1_availability,
            },

            {
                .name = "CLIPPER OUTPUT READY SLICE1",
                .symbol_name = "CLIPPER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Clipper output ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__clipper_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_CLIPPER_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "CLIPPER PRIMITIVE OUTPUT SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_OUTPUT_SLICE1",
                .desc = "Number of primitives going out of Clipper, must clip plus the trivial accept",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext125__clipper_primitive_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext125_CLIPPER_PRIMITIVE_OUTPUT_SLICE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext125__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext125__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE2",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__ps_output_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_PS_OUTPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PS OUTPUT AVAILABLE CPIPE3",
                .symbol_name = "PS_OUTPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Pixel Shader data is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__ps_output_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_PS_OUTPUT_AVAILABLE_CPIPE3_availability,
            },

            {
                .name = "STREAMOUT OUTPUT VERTEX COUNT SLICE1",
                .symbol_name = "STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1",
                .desc = "Number of vertices written by SOL",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext125__streamout_output_vertex_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext125_STREAMOUT_OUTPUT_VERTEX_COUNT_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OUTPUT READY SLICE1",
                .symbol_name = "STRIPSFAN_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which in which geometry pipeline output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__stripsfan_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_STRIPSFAN_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH INPUT AVAILABLE SLICE1",
                .symbol_name = "VERTEX_FETCH_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__vertex_fetch_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_VERTEX_FETCH_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "VERTEX FETCH OUTPUT READY SLICE1",
                .symbol_name = "VERTEX_FETCH_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Fetch output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__vertex_fetch_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_VERTEX_FETCH_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "VS OUTPUT READY SLICE1",
                .symbol_name = "VS_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Vertex Shader output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext125__vs_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext125_VS_OUTPUT_READY_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 14);
}

static bool mtlgt3_ext126_CLIPPER_PRIMITIVE_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext126_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext126_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext126_RASTERIZER_OUTPUT_READY_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext126_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext126_STRIPSFAN_OBJECTS_CULL_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext126_STRIPSFAN_OBJECT_COUNT_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext126_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext126";
    metric_set->symbol_name = "Ext126";
    metric_set->hw_config_guid = "9a0ec3ea-1d61-413e-8b9c-169cdec1f9b3";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext126_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext126__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext126__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE0",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE0",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext126__clipper_primitive_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext126_CLIPPER_PRIMITIVE_CULL_SLICE0_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext126__clipper_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext126_CLIPPER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext126__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext126__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE0",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE0",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext126__rasterizer_input_available_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext126_RASTERIZER_INPUT_AVAILABLE_SLICE0_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE0",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE0",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext126__rasterizer_output_ready_slice0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext126_RASTERIZER_OUTPUT_READY_SLICE0_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE0",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE0",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext126__rasterizer_transaction_output_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext126_RASTERIZER_TRANSACTION_OUTPUT_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE0",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE0",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext126__stripsfan_objects_cull_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext126_STRIPSFAN_OBJECTS_CULL_SLICE0_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE0",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE0",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext126__stripsfan_object_count_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext126_STRIPSFAN_OBJECT_COUNT_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext127_CLIPPER_PRIMITIVE_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext127_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext127_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext127_RASTERIZER_OUTPUT_READY_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext127_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext127_STRIPSFAN_OBJECTS_CULL_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext127_STRIPSFAN_OBJECT_COUNT_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext127_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext127";
    metric_set->symbol_name = "Ext127";
    metric_set->hw_config_guid = "1f70ab0a-6efd-461b-b06e-3b47d3602f36";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext127_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext127__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext127__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "CLIPPER PRIMITIVE CULL SLICE1",
                .symbol_name = "CLIPPER_PRIMITIVE_CULL_SLICE1",
                .desc = "Number of Clipper early cull primitives",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext127__clipper_primitive_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext127_CLIPPER_PRIMITIVE_CULL_SLICE1_availability,
            },

            {
                .name = "CLIPPER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "CLIPPER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of elements pushed by Clipper into Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext127__clipper_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext127_CLIPPER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext127__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext127__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RASTERIZER INPUT AVAILABLE SLICE1",
                .symbol_name = "RASTERIZER_INPUT_AVAILABLE_SLICE1",
                .desc = "Percentage of time in which Rasterizer input is available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext127__rasterizer_input_available_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext127_RASTERIZER_INPUT_AVAILABLE_SLICE1_availability,
            },

            {
                .name = "RASTERIZER OUTPUT READY SLICE1",
                .symbol_name = "RASTERIZER_OUTPUT_READY_SLICE1",
                .desc = "Percentage of time in which Rasterizer output is ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext127__rasterizer_output_ready_slice1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext127_RASTERIZER_OUTPUT_READY_SLICE1_availability,
            },

            {
                .name = "RASTERIZER TRANSACTION OUTPUT SLICE1",
                .symbol_name = "RASTERIZER_TRANSACTION_OUTPUT_SLICE1",
                .desc = "Number of transactions pushed from Rasterizer to the Z pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext127__rasterizer_transaction_output_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext127_RASTERIZER_TRANSACTION_OUTPUT_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECTS CULL SLICE1",
                .symbol_name = "STRIPSFAN_OBJECTS_CULL_SLICE1",
                .desc = "Number of simple culled objects in Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext127__stripsfan_objects_cull_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext127_STRIPSFAN_OBJECTS_CULL_SLICE1_availability,
            },

            {
                .name = "STRIPSFAN OBJECT COUNT SLICE1",
                .symbol_name = "STRIPSFAN_OBJECT_COUNT_SLICE1",
                .desc = "Number of objects exiting Stripsfan stage",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext127__stripsfan_object_count_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext127_STRIPSFAN_OBJECT_COUNT_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext128_URB_CROSS_SLICE_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext128_URB_READ_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext128_URB_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext128_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext128";
    metric_set->symbol_name = "Ext128";
    metric_set->hw_config_guid = "9eedb03f-340b-40ec-8a66-43d01973003e";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext128_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext128__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext128__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext128__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext128__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE0",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE0",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext128__urb_cross_slice_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext128_URB_CROSS_SLICE_READ_SLICE0_availability,
            },

            {
                .name = "URB READ SLICE0",
                .symbol_name = "URB_READ_SLICE0",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext128__urb_read_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext128_URB_READ_SLICE0_availability,
            },

            {
                .name = "URB WRITE SLICE0",
                .symbol_name = "URB_WRITE_SLICE0",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext128__urb_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext128_URB_WRITE_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool mtlgt3_ext129_URB_CROSS_SLICE_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext129_URB_READ_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext129_URB_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext129_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext129";
    metric_set->symbol_name = "Ext129";
    metric_set->hw_config_guid = "0e5ffe58-83b2-445b-a439-9ee7a01642d4";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext129_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext129__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext129__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext129__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext129__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "URB CROSS SLICE READ SLICE1",
                .symbol_name = "URB_CROSS_SLICE_READ_SLICE1",
                .desc = "Number of URB reads occurred from cross slices",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext129__urb_cross_slice_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext129_URB_CROSS_SLICE_READ_SLICE1_availability,
            },

            {
                .name = "URB READ SLICE1",
                .symbol_name = "URB_READ_SLICE1",
                .desc = "Number of URB reads",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext129__urb_read_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext129_URB_READ_SLICE1_availability,
            },

            {
                .name = "URB WRITE SLICE1",
                .symbol_name = "URB_WRITE_SLICE1",
                .desc = "Number of URB writes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext129__urb_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext129_URB_WRITE_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool mtlgt3_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext130_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext130";
    metric_set->symbol_name = "Ext130";
    metric_set->hw_config_guid = "78925a28-3e52-4d74-b03b-cb27c6a4401a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext130_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext130__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext130__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext130__early_depth_stencil_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE0_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE0",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext130__early_depth_stencil_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext130_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE0_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext130__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext130__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext131_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext131";
    metric_set->symbol_name = "Ext131";
    metric_set->hw_config_guid = "1e91d8d9-ced4-4240-bf9e-fdd7d015c058";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext131_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext131__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext131__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext131__early_depth_stencil_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE1_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE1",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext131__early_depth_stencil_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext131_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE1_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext131__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext131__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext132_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext132";
    metric_set->symbol_name = "Ext132";
    metric_set->hw_config_guid = "1cacf022-b4d4-401c-abec-acc0a3353adc";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext132_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext132__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext132__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext132__early_depth_stencil_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE2_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE2",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext132__early_depth_stencil_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext132_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE2_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext132__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext132__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext133_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext133";
    metric_set->symbol_name = "Ext133";
    metric_set->hw_config_guid = "3c15657a-b3da-4513-8b9c-08bcc1ca0226";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext133_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext133__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext133__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL NP ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed Depth / Stencil before the Pixel Shader that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext133__early_depth_stencil_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_NP_ZPIPE3_availability,
            },

            {
                .name = "EARLY DEPTH STENCIL TEST FAIL P ZPIPE3",
                .symbol_name = "EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed Depth / Stencil that were previously ambiguous at HiZ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext133__early_depth_stencil_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext133_EARLY_DEPTH_STENCIL_TEST_FAIL_P_ZPIPE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext133__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext133__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext134_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext134_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext134";
    metric_set->symbol_name = "Ext134";
    metric_set->hw_config_guid = "da34c79f-d1c6-4d15-b848-2085528bb86b";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext134_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext134__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext134__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext134__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext134__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext134__hiz_depth_test_ambig_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext134_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext135_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext135_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext135";
    metric_set->symbol_name = "Ext135";
    metric_set->hw_config_guid = "33ceab81-26bc-49f3-a124-5dbb2d592a87";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext135_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext135__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext135__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext135__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext135__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext135__hiz_depth_test_ambig_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext135_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext136_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext136_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext136";
    metric_set->symbol_name = "Ext136";
    metric_set->hw_config_guid = "d8b7d2f7-7c3a-4a68-b6c1-48d197b22945";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext136_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext136__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext136__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext136__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext136__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext136__hiz_depth_test_ambig_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext136_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext137_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext137_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext137";
    metric_set->symbol_name = "Ext137";
    metric_set->hw_config_guid = "01d6bd34-b8d1-4412-b53b-0d16b327abec";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext137_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext137__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext137__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext137__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext137__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext137__hiz_depth_test_ambig_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext137_HIZ_DEPTH_TEST_AMBIG_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext138_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext138_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext138";
    metric_set->symbol_name = "Ext138";
    metric_set->hw_config_guid = "7485f9ec-ac5f-4c6d-8c5f-6a023e7d29d5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext138_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext138__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext138__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext138__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext138__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext138__hiz_depth_test_ambig_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext138_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext139_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext139_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext139";
    metric_set->symbol_name = "Ext139";
    metric_set->hw_config_guid = "944dc12b-b2fd-4bf5-a59d-540e2b280cdd";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext139_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext139__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext139__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext139__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext139__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext139__hiz_depth_test_ambig_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext139_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext140_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext140_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext140";
    metric_set->symbol_name = "Ext140";
    metric_set->hw_config_guid = "5c97330a-b407-4ef8-908f-7fdeec216f81";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext140_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext140__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext140__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext140__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext140__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext140__hiz_depth_test_ambig_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext140_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext141_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext141_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext141";
    metric_set->symbol_name = "Ext141";
    metric_set->hw_config_guid = "65e4ac2a-db8f-4918-bdd6-ac4d85de160e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext141_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext141__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext141__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext141__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext141__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST AMBIG P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that are ambiguous by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext141__hiz_depth_test_ambig_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext141_HIZ_DEPTH_TEST_AMBIG_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext142_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext142_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext142";
    metric_set->symbol_name = "Ext142";
    metric_set->hw_config_guid = "0eb11775-ad71-44d4-ad2c-c2fa6431b144";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext142_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext142__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext142__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext142__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext142__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext142__hiz_depth_test_fail_np_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext142_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext143_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext143_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext143";
    metric_set->symbol_name = "Ext143";
    metric_set->hw_config_guid = "d7736d53-f1cb-4899-8f3d-d8aaad1f1c67";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext143_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext143__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext143__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext143__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext143__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext143__hiz_depth_test_fail_np_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext143_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext144_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext144_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext144";
    metric_set->symbol_name = "Ext144";
    metric_set->hw_config_guid = "496219cc-316b-4945-9fc4-180e60331262";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext144_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext144__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext144__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext144__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext144__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext144__hiz_depth_test_fail_np_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext144_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext145_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext145_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext145";
    metric_set->symbol_name = "Ext145";
    metric_set->hw_config_guid = "c7e6721e-51f9-40af-ba8b-0520a1082855";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext145_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext145__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext145__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext145__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext145__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL NP ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3",
                .desc = "Number of non-promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext145__hiz_depth_test_fail_np_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext145_HIZ_DEPTH_TEST_FAIL_NP_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext146_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext146_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext146";
    metric_set->symbol_name = "Ext146";
    metric_set->hw_config_guid = "0e9b064c-9fa7-4e85-8aaa-cc871010117d";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext146_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext146__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext146__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext146__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext146__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE0",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext146__hiz_depth_test_fail_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext146_HIZ_DEPTH_TEST_FAIL_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext147_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext147_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext147";
    metric_set->symbol_name = "Ext147";
    metric_set->hw_config_guid = "44d73f02-f843-4717-a3d5-3d1dfbd3f106";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext147_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext147__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext147__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext147__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext147__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE1",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext147__hiz_depth_test_fail_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext147_HIZ_DEPTH_TEST_FAIL_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext148_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext148_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext148";
    metric_set->symbol_name = "Ext148";
    metric_set->hw_config_guid = "b84f370e-1b64-41d1-a4d8-f095fb79e5f8";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext148_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext148__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext148__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext148__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext148__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE2",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext148__hiz_depth_test_fail_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext148_HIZ_DEPTH_TEST_FAIL_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext149_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext149_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext149";
    metric_set->symbol_name = "Ext149";
    metric_set->hw_config_guid = "772a2c24-0a03-480e-baca-72f2f55a5422";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext149_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext149__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext149__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext149__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext149__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST FAIL P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_FAIL_P_ZPIPE3",
                .desc = "Number of promoted 2x2 that failed the hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext149__hiz_depth_test_fail_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext149_HIZ_DEPTH_TEST_FAIL_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext150_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext150_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext150";
    metric_set->symbol_name = "Ext150";
    metric_set->hw_config_guid = "953d3bf8-af3d-4287-ac22-dcd122c5eb51";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext150_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext150__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext150__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext150__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext150__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE0",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE0",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext150__hiz_depth_test_pass_p_zpipe0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext150_HIZ_DEPTH_TEST_PASS_P_ZPIPE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext151_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext151_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext151";
    metric_set->symbol_name = "Ext151";
    metric_set->hw_config_guid = "dbb009c2-98ad-4af0-905a-e7808ac5424c";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext151_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext151__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext151__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext151__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext151__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE1",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE1",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext151__hiz_depth_test_pass_p_zpipe1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext151_HIZ_DEPTH_TEST_PASS_P_ZPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext152_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext152_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext152";
    metric_set->symbol_name = "Ext152";
    metric_set->hw_config_guid = "16fd8981-676d-4cbc-b010-8d731ba66a06";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext152_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext152__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext152__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext152__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext152__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE2",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE2",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext152__hiz_depth_test_pass_p_zpipe2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext152_HIZ_DEPTH_TEST_PASS_P_ZPIPE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext153_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext153_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext153";
    metric_set->symbol_name = "Ext153";
    metric_set->hw_config_guid = "7bcdd766-98a5-461a-ac8e-d8c648958364";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext153_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext153__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext153__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext153__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext153__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ DEPTH TEST PASS P ZPIPE3",
                .symbol_name = "HIZ_DEPTH_TEST_PASS_P_ZPIPE3",
                .desc = "Number of promoted 2x2 passed by hierarchical depth test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext153__hiz_depth_test_pass_p_zpipe3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext153_HIZ_DEPTH_TEST_PASS_P_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext154_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext154";
    metric_set->symbol_name = "Ext154";
    metric_set->hw_config_guid = "c0459fa8-1790-46b8-a0f8-3064baf7c670";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext154_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext154__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext154__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext154__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext154__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "HIZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which HiZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__hiz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_HIZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE0",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE0",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_output_ready_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE0_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE1",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE1",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_output_ready_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE1_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE2",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE2",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_output_ready_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE2_availability,
            },

            {
                .name = "IZ OUTPUT READY ZPIPE3",
                .symbol_name = "IZ_OUTPUT_READY_ZPIPE3",
                .desc = "Percentage of time in which IZ has requests to different clients",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_output_ready_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_OUTPUT_READY_ZPIPE3_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE0",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE0_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE1",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE1_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE2",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE2_availability,
            },

            {
                .name = "IZ SUBSPAN LATENCY FIFOFULL ZPIPE3",
                .symbol_name = "IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3",
                .desc = "Percentage of time in which IZ latency hiding structure full",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext154__iz_subspan_latency_fifofull_zpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext154_IZ_SUBSPAN_LATENCY_FIFOFULL_ZPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}


static void
mtlgt3_add_ext155_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext155";
    metric_set->symbol_name = "Ext155";
    metric_set->hw_config_guid = "304d9439-4bdd-48a9-a82e-15b3533afaf4";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext155_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext155__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext155__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE BUSY CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_BUSY_CCS0",
                .desc = "Percentage of time in which there is a context loaded and active on the compute queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext155__command_parser_compute_engine_busy_ccs0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COPY ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_COPY_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the copy queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext155__command_parser_copy_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE BUSY",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the 3D queue",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext155__command_parser_render_engine_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext155__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext155__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}


static void
mtlgt3_add_ext156_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext156";
    metric_set->symbol_name = "Ext156";
    metric_set->hw_config_guid = "90691d58-782d-459c-a242-f6e515fe9567";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext156_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext156__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext156__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER COMPUTE ENGINE DISPATCH KERNEL COUNT CCS0",
                .symbol_name = "COMMAND_PARSER_COMPUTE_ENGINE_DISPATCH_KERNEL_COUNT_CCS0",
                .desc = "Number of compute walker commands parsed on the compute engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext156__command_parser_compute_engine_dispatch_kernel_count_ccs0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER FLUSH COUNT",
                .symbol_name = "COMMAND_PARSER_FLUSH_COUNT",
                .desc = "Number of Stalling flushes at the top of the pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext156__command_parser_flush_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DISPATCH KERNEL COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DISPATCH_KERNEL_COUNT",
                .desc = "Number of compute walker commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext156__command_parser_render_engine_dispatch_kernel_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER RENDER ENGINE DRAW COUNT",
                .symbol_name = "COMMAND_PARSER_RENDER_ENGINE_DRAW_COUNT",
                .desc = "Number of DRAW and MESH commands parsed on the 3D engine",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext156__command_parser_render_engine_draw_count__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext156__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext156__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext158_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext158";
    metric_set->symbol_name = "Ext158";
    metric_set->hw_config_guid = "cf34a431-3cc9-4b70-a84e-0d31a71170f0";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext158_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext158__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext158__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext158__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext158__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE0",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE0",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE1",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE1",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE2",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE2",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE3",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE3",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE4",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE4",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE5",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE5",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE6",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE6",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT INPUT MESSAGE RAY COUNT XECORE7",
                .symbol_name = "RT_INPUT_MESSAGE_RAY_COUNT_XECORE7",
                .desc = "Number of valid SIMD lanes in the TraceRay message",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext158__rt_input_message_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext158_RT_INPUT_MESSAGE_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext159_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext159";
    metric_set->symbol_name = "Ext159";
    metric_set->hw_config_guid = "ad3cd014-8897-4613-8653-6d80c6eaff88";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext159_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext159__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext159__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext159__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext159__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext159__rt_closest_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext159_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext160_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext160";
    metric_set->symbol_name = "Ext160";
    metric_set->hw_config_guid = "aa12de63-7d11-4acf-af96-be89807729f7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext160_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext160__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext160__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext160__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext160__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CLOSEST HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of closest hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext160__rt_closest_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext160_RT_CLOSEST_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext161_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext161";
    metric_set->symbol_name = "Ext161";
    metric_set->hw_config_guid = "ac013132-7e0c-4143-bc34-ea6428ce3082";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext161_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext161__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext161__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext161__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext161__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext161__rt_miss_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext161_RT_MISS_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext162_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext162";
    metric_set->symbol_name = "Ext162";
    metric_set->hw_config_guid = "b9d8323a-7bb4-41b5-b99b-43ed99e23590";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext162_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext162__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext162__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext162__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext162__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT MISS THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_MISS_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of miss threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext162__rt_miss_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext162_RT_MISS_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext163_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext163";
    metric_set->symbol_name = "Ext163";
    metric_set->hw_config_guid = "6ae2c19e-672c-4ad6-9d59-0a391af1af4f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext163_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext163__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext163__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext163__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext163__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext163__rt_any_hit_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext163_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext164_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext164";
    metric_set->symbol_name = "Ext164";
    metric_set->hw_config_guid = "c76b6b40-9d7f-48f6-b6da-595252c884f4";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext164_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext164__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext164__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext164__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext164__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT ANY HIT THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of any hit threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext164__rt_any_hit_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext164_RT_ANY_HIT_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext165_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext165";
    metric_set->symbol_name = "Ext165";
    metric_set->hw_config_guid = "a85da4d8-d984-45f3-8dbe-c8678eac8aae";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext165_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext165__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext165__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext165__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext165__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext165__rt_intersection_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext165_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext166_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext166";
    metric_set->symbol_name = "Ext166";
    metric_set->hw_config_guid = "fbc7362e-4d05-451d-833e-f0ce5e7ad8e3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext166_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext166__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext166__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext166__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext166__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT INTERSECTION THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of intersection threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext166__rt_intersection_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext166_RT_INTERSECTION_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext167_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext167";
    metric_set->symbol_name = "Ext167";
    metric_set->hw_config_guid = "881454da-d271-41ba-9dfb-0cc354fb5aea";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext167_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext167__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext167__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext167__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext167__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE0",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE0_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE1",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE1_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE2",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE2_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE3",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext167__rt_callable_thread_ray_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext167_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext168_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext168";
    metric_set->symbol_name = "Ext168";
    metric_set->hw_config_guid = "9f2b827b-01c6-4e82-b283-dfe91af30d88";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext168_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext168__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext168__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext168__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext168__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE4",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE4_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE5",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE5_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE6",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE6_availability,
            },

            {
                .name = "RT CALLABLE THREAD RAY DISPATCH XECORE7",
                .symbol_name = "RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7",
                .desc = "Number of callable threads dispatched for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext168__rt_callable_thread_ray_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext168_RT_CALLABLE_THREAD_RAY_DISPATCH_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext169_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext169";
    metric_set->symbol_name = "Ext169";
    metric_set->hw_config_guid = "c6b40da2-4783-45d7-8252-9a4f1f75faf4";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext169_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext169__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext169__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext169__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext169__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext169__rt_traversal_output_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext169__rt_traversal_output_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext169__rt_traversal_output_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext169__rt_traversal_output_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext169_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext170_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext170";
    metric_set->symbol_name = "Ext170";
    metric_set->hw_config_guid = "b5883529-3595-412d-b40f-b7ade9cc3304";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext170_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext170__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext170__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext170__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext170__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext170__rt_traversal_output_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext170__rt_traversal_output_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext170__rt_traversal_output_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL OUTPUT RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7",
                .desc = "Number of Ray Tracing Traversal output rays",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext170__rt_traversal_output_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext170_RT_TRAVERSAL_OUTPUT_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext171_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext171";
    metric_set->symbol_name = "Ext171";
    metric_set->hw_config_guid = "2455c20b-95bb-4e9f-8db2-597ba9447025";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext171_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext171__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext171__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext171__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext171__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE0",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE0",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext171__rt_message_stall_count_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE0_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE1",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE1",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext171__rt_message_stall_count_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE1_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE2",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE2",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext171__rt_message_stall_count_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE2_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE3",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE3",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext171__rt_message_stall_count_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_MESSAGE_STALL_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE0",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_quad_test_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE1",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_quad_test_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE2",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_quad_test_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE3",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_quad_test_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_QUAD_TEST_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE0",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE0",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_request_collision_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE0_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE1",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE1",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_request_collision_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE1_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE2",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE2",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_request_collision_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE2_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE3",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE3",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_request_collision_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_REQUEST_COLLISION_XECORE3_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE0",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE0",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_transform_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE1",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE1",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_transform_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE2",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE2",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_transform_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE3",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE3",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext171__rt_transform_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext171_RT_TRANSFORM_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext172_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext172";
    metric_set->symbol_name = "Ext172";
    metric_set->hw_config_guid = "ec18cd0b-7caa-48d0-9a16-418ecbe1096e";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext172_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext172__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext172__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext172__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext172__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE4",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE4",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext172__rt_message_stall_count_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE4_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE5",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE5",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext172__rt_message_stall_count_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE5_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE6",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE6",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext172__rt_message_stall_count_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE6_availability,
            },

            {
                .name = "RT MESSAGE STALL COUNT XECORE7",
                .symbol_name = "RT_MESSAGE_STALL_COUNT_XECORE7",
                .desc = "Percentage of time in which Ray Tracing message input is stalled while accepting input",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext172__rt_message_stall_count_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_MESSAGE_STALL_COUNT_XECORE7_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE4",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_quad_test_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE5",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_quad_test_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE6",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_quad_test_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD TEST RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_TEST_RAY_COUNT_XECORE7",
                .desc = "Number of nodes processed that use ray-quad intersection pipeline",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_quad_test_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_QUAD_TEST_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE4",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE4",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_request_collision_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE4_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE5",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE5",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_request_collision_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE5_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE6",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE6",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_request_collision_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE6_availability,
            },

            {
                .name = "RT REQUEST COLLISION XECORE7",
                .symbol_name = "RT_REQUEST_COLLISION_XECORE7",
                .desc = "Percentage of time in which RayTracing Leaf has two Traversal inputs valid",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_request_collision_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_REQUEST_COLLISION_XECORE7_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE4",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE4",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_transform_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE5",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE5",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_transform_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE6",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE6",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_transform_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRANSFORM RAY COUNT XECORE7",
                .symbol_name = "RT_TRANSFORM_RAY_COUNT_XECORE7",
                .desc = "Number of only HW transform accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext172__rt_transform_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext172_RT_TRANSFORM_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext173_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext173_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext173_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext173_XVE_STALL_CONTROL_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext173_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext173_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext173_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext173_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext173";
    metric_set->symbol_name = "Ext173";
    metric_set->hw_config_guid = "3628b2de-d9f9-4db2-a74f-32a314e591c5";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext173_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext173__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext173__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext173__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext173__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext173__xve_shared_function_access_hold_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext173_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext173__xve_stall_aluwr_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext173_XVE_STALL_ALUWR_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext173__xve_stall_barrier_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext173_XVE_STALL_BARRIER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext173__xve_stall_control_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext173_XVE_STALL_CONTROL_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext173__xve_stall_instfetch_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext173_XVE_STALL_INSTFETCH_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext173__xve_stall_other_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext173_XVE_STALL_OTHER_XECORE0_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE0 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE0_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext173__xve_stall_sbid_xecore0_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext173_XVE_STALL_SBID_XECORE0_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext174_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext174_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext174_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext174_XVE_STALL_CONTROL_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext174_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext174_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext174_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext174_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext174";
    metric_set->symbol_name = "Ext174";
    metric_set->hw_config_guid = "d35ecd39-0a9d-48f7-bf87-d3c318b8fadd";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext174_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext174__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext174__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext174__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext174__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext174__xve_shared_function_access_hold_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext174_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext174__xve_stall_aluwr_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext174_XVE_STALL_ALUWR_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext174__xve_stall_barrier_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext174_XVE_STALL_BARRIER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext174__xve_stall_control_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext174_XVE_STALL_CONTROL_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext174__xve_stall_instfetch_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext174_XVE_STALL_INSTFETCH_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext174__xve_stall_other_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext174_XVE_STALL_OTHER_XECORE1_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE1 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE1_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext174__xve_stall_sbid_xecore1_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext174_XVE_STALL_SBID_XECORE1_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext175_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext175_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext175_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext175_XVE_STALL_CONTROL_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext175_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext175_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext175_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext175_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext175";
    metric_set->symbol_name = "Ext175";
    metric_set->hw_config_guid = "d0d0e9cc-494c-4b01-8a43-683aae5beaff";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext175_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext175__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext175__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext175__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext175__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext175__xve_shared_function_access_hold_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext175_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext175__xve_stall_aluwr_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext175_XVE_STALL_ALUWR_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext175__xve_stall_barrier_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext175_XVE_STALL_BARRIER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext175__xve_stall_control_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext175_XVE_STALL_CONTROL_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext175__xve_stall_instfetch_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext175_XVE_STALL_INSTFETCH_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext175__xve_stall_other_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext175_XVE_STALL_OTHER_XECORE2_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE2 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE2_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext175__xve_stall_sbid_xecore2_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext175_XVE_STALL_SBID_XECORE2_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext176_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext176_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext176_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext176_XVE_STALL_CONTROL_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext176_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext176_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext176_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext176_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext176";
    metric_set->symbol_name = "Ext176";
    metric_set->hw_config_guid = "c5fde834-52c8-411b-854e-8d3197def109";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext176_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext176__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext176__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext176__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext176__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext176__xve_shared_function_access_hold_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext176_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext176__xve_stall_aluwr_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext176_XVE_STALL_ALUWR_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext176__xve_stall_barrier_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext176_XVE_STALL_BARRIER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext176__xve_stall_control_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext176_XVE_STALL_CONTROL_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext176__xve_stall_instfetch_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext176_XVE_STALL_INSTFETCH_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext176__xve_stall_other_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext176_XVE_STALL_OTHER_XECORE3_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE3 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE3_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext176__xve_stall_sbid_xecore3_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext176_XVE_STALL_SBID_XECORE3_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext177_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext177_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext177_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext177_XVE_STALL_CONTROL_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext177_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext177_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext177_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext177_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext177";
    metric_set->symbol_name = "Ext177";
    metric_set->hw_config_guid = "55830ebd-062b-40e8-8d5c-e921429957ff";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext177_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext177__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext177__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext177__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext177__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext177__xve_shared_function_access_hold_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext177_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext177__xve_stall_aluwr_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext177_XVE_STALL_ALUWR_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext177__xve_stall_barrier_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext177_XVE_STALL_BARRIER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext177__xve_stall_control_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext177_XVE_STALL_CONTROL_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext177__xve_stall_instfetch_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext177_XVE_STALL_INSTFETCH_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext177__xve_stall_other_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext177_XVE_STALL_OTHER_XECORE4_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE4 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE4_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext177__xve_stall_sbid_xecore4_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext177_XVE_STALL_SBID_XECORE4_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext178_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext178_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext178_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext178_XVE_STALL_CONTROL_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext178_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext178_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext178_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext178_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext178";
    metric_set->symbol_name = "Ext178";
    metric_set->hw_config_guid = "9603d88f-e5bf-47b4-85fd-fbbb68f42632";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext178_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext178__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext178__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext178__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext178__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext178__xve_shared_function_access_hold_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext178_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext178__xve_stall_aluwr_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext178_XVE_STALL_ALUWR_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext178__xve_stall_barrier_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext178_XVE_STALL_BARRIER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext178__xve_stall_control_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext178_XVE_STALL_CONTROL_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext178__xve_stall_instfetch_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext178_XVE_STALL_INSTFETCH_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext178__xve_stall_other_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext178_XVE_STALL_OTHER_XECORE5_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE5 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE5_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext178__xve_stall_sbid_xecore5_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext178_XVE_STALL_SBID_XECORE5_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext179_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext179_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext179_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext179_XVE_STALL_CONTROL_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext179_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext179_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext179_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext179_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext179";
    metric_set->symbol_name = "Ext179";
    metric_set->hw_config_guid = "b05bd7bd-387f-4fd7-a1b4-06a1dab5bc14";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext179_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext179__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext179__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext179__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext179__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext179__xve_shared_function_access_hold_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext179_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext179__xve_stall_aluwr_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext179_XVE_STALL_ALUWR_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext179__xve_stall_barrier_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext179_XVE_STALL_BARRIER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext179__xve_stall_control_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext179_XVE_STALL_CONTROL_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext179__xve_stall_instfetch_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext179_XVE_STALL_INSTFETCH_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext179__xve_stall_other_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext179_XVE_STALL_OTHER_XECORE6_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE6 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE6_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext179__xve_stall_sbid_xecore6_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext179_XVE_STALL_SBID_XECORE6_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext180_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext180_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext180_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext180_XVE_STALL_CONTROL_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext180_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext180_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext180_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext180_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext180";
    metric_set->symbol_name = "Ext180";
    metric_set->hw_config_guid = "49dc9023-be7b-4102-a4a2-d31b9a6b1ce4";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext180_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext180__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext180__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext180__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext180__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE SHARED FUNCTION ACCESS HOLD XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE requests stalled by Shared Function units",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext180__xve_shared_function_access_hold_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext180_XVE_SHARED_FUNCTION_ACCESS_HOLD_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL ALUWR XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for ALU to write GRF/ACC register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext180__xve_stall_aluwr_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext180_XVE_STALL_ALUWR_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL BARRIER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Gateway to write Notify register",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext180__xve_stall_barrier_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext180_XVE_STALL_BARRIER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL CONTROL XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_CONTROL_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for JEU to complete branch instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext180__xve_stall_control_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext180_XVE_STALL_CONTROL_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL INSTFETCH XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Instruction Fetch",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext180__xve_stall_instfetch_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext180_XVE_STALL_INSTFETCH_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL OTHER XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_OTHER_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting on any other dependency (Flag/EoT etc)",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext180__xve_stall_other_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext180_XVE_STALL_OTHER_XECORE7_XVE0_THREAD0_availability,
            },

            {
                .name = "XVE STALL SBID XECORE7 XVE0 THREAD0",
                .symbol_name = "XVE_STALL_SBID_XECORE7_XVE0_THREAD0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread waiting for Scoreboard token to be available",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext180__xve_stall_sbid_xecore7_xve0_thread0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext180_XVE_STALL_SBID_XECORE7_XVE0_THREAD0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}

static bool mtlgt3_ext181_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext181_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext181_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext181_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext181";
    metric_set->symbol_name = "Ext181";
    metric_set->hw_config_guid = "871d8a6b-7c73-4cd7-a4ed-4bdb58d5b6ee";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext181_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext181__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext181__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext181__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext181__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE0 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE0_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext181__xve_inst_issued_all_xecore0_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext181_XVE_INST_ISSUED_ALL_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE1 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE1_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext181__xve_inst_issued_all_xecore1_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext181_XVE_INST_ISSUED_ALL_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE2 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE2_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext181__xve_inst_issued_all_xecore2_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext181_XVE_INST_ISSUED_ALL_XECORE2_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool mtlgt3_ext182_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext182_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext182_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext182_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext182";
    metric_set->symbol_name = "Ext182";
    metric_set->hw_config_guid = "25a2f80d-147e-4363-a0cb-53584b7a837d";
    metric_set->counters = calloc(6, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext182_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext182__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext182__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext182__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext182__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST ISSUED ALL XECORE4 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE4_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext182__xve_inst_issued_all_xecore4_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext182_XVE_INST_ISSUED_ALL_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE5 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE5_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext182__xve_inst_issued_all_xecore5_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext182_XVE_INST_ISSUED_ALL_XECORE5_XVE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE6 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE6_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext182__xve_inst_issued_all_xecore6_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext182_XVE_INST_ISSUED_ALL_XECORE6_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 6);
}

static bool mtlgt3_ext183_RENDER_CACHE_ALLOC_L3NODE0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext183_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext183_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext183";
    metric_set->symbol_name = "Ext183";
    metric_set->hw_config_guid = "71863fcf-d57c-433b-858f-87f5f11ec3da";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext183_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext183__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext183__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext183__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext183__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE0",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE0",
                .desc = "Number of Render Cache allocations - cache miss signal for new allocation",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext183__render_cache_alloc_l3_node0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext183_RENDER_CACHE_ALLOC_L3NODE0_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE3 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE3_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext183__xve_inst_issued_all_xecore3_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext183_XVE_INST_ISSUED_ALL_XECORE3_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE0 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE0_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext183__xve_stall_pipestall_xecore0_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE1 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE1_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext183__xve_stall_pipestall_xecore1_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE2 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE2_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext183__xve_stall_pipestall_xecore2_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE2_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE3 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE3_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext183__xve_stall_pipestall_xecore3_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext183_XVE_STALL_PIPESTALL_XECORE3_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool mtlgt3_ext184_RENDER_CACHE_ALLOC_L3NODE1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext184_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext184_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext184";
    metric_set->symbol_name = "Ext184";
    metric_set->hw_config_guid = "c29640d9-39eb-4a03-9043-2a54eb5a3112";
    metric_set->counters = calloc(9, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext184_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext184__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext184__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext184__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext184__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RENDER CACHE ALLOC L3NODE1",
                .symbol_name = "RENDER_CACHE_ALLOC_L3NODE1",
                .desc = "Number of Render Cache allocations - cache miss signal for new allocation",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext184__render_cache_alloc_l3_node1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext184_RENDER_CACHE_ALLOC_L3NODE1_availability,
            },

            {
                .name = "XVE INST ISSUED ALL XECORE7 XVE0",
                .symbol_name = "XVE_INST_ISSUED_ALL_XECORE7_XVE0",
                .desc = "Number of instructions issued (decoded) to any pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext184__xve_inst_issued_all_xecore7_xve0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext184_XVE_INST_ISSUED_ALL_XECORE7_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE4 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE4_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext184__xve_stall_pipestall_xecore4_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE5 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE5_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext184__xve_stall_pipestall_xecore5_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE5_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE6 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE6_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext184__xve_stall_pipestall_xecore6_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE STALL PIPESTALL XECORE7 XVE0",
                .symbol_name = "XVE_STALL_PIPESTALL_XECORE7_XVE0",
                .desc = "Percentage of time in which XVE stalled, with at least one thread is ready to be scheduled",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext184__xve_stall_pipestall_xecore7_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext184_XVE_STALL_PIPESTALL_XECORE7_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 9);
}

static bool mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext185_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext185";
    metric_set->symbol_name = "Ext185";
    metric_set->hw_config_guid = "00882747-d1dd-4ba5-9b72-96df25dad7bd";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext185_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext185__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext185__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext185__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext185__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext185__rt_load_store_cache_read_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext185_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext186_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext186";
    metric_set->symbol_name = "Ext186";
    metric_set->hw_config_guid = "89aea44f-ffa6-43cc-9a9c-103b4930e103";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext186_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext186__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext186__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext186__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext186__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE READ MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7",
                .desc = "Number of read messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext186__rt_load_store_cache_read_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext186_RT_LOAD_STORE_CACHE_READ_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext188_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext188";
    metric_set->symbol_name = "Ext188";
    metric_set->hw_config_guid = "11e92a4a-d605-499c-9159-e79797c230de";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext188_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext188__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext188__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext188__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext188__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE0",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE1",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE2",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE3",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext188__rt_load_store_cache_write_from_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext188_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext189_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext189";
    metric_set->symbol_name = "Ext189";
    metric_set->hw_config_guid = "27c2ef51-6689-4ffc-acaa-3f46a8e834cf";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext189_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext189__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext189__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext189__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext189__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE4",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE5",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE6",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "RT LOAD STORE CACHE WRITE FROM MESSAGE COUNT XECORE7",
                .symbol_name = "RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7",
                .desc = "Number of write messages sent from Ray Tracing unit to the Load Store Cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext189__rt_load_store_cache_write_from_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext189_RT_LOAD_STORE_CACHE_WRITE_FROM_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext190_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext190_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext190_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext190";
    metric_set->symbol_name = "Ext190";
    metric_set->hw_config_guid = "1625df84-2f24-4aed-9ced-e652184c9949";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext190_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext190__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext190__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext190__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext190__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE0",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext190__pixel_post_process_input_available_cpipe0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext190_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE0_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE1",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext190__pixel_post_process_input_available_cpipe1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext190_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext191_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext191_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext191_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext191";
    metric_set->symbol_name = "Ext191";
    metric_set->hw_config_guid = "d98e7947-ecee-46a9-b3ac-619d13d32b1a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext191_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext191__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext191__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext191__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext191__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE2",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext191__pixel_post_process_input_available_cpipe2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext191_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE2_availability,
            },

            {
                .name = "PIXEL POST PROCESS INPUT AVAILABLE CPIPE3",
                .symbol_name = "PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3",
                .desc = "Percentage of time in which Color Pipeline input ready",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext191__pixel_post_process_input_available_cpipe3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext191_PIXEL_POST_PROCESS_INPUT_AVAILABLE_CPIPE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext192_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext192";
    metric_set->symbol_name = "Ext192";
    metric_set->hw_config_guid = "ed973589-e13c-4115-a2b1-08bc443a4e8d";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext192_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext192__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext192__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext192__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext192__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE0",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE0",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext192__rt_input_available_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE0_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE1",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE1",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext192__rt_input_available_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE1_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE2",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE2",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext192__rt_input_available_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE2_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE3",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE3",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext192__rt_input_available_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_INPUT_AVAILABLE_XECORE3_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE0",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext192__rt_traversal_step_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE1",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext192__rt_traversal_step_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE2",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext192__rt_traversal_step_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE3",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext192__rt_traversal_step_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext192_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext193_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext193";
    metric_set->symbol_name = "Ext193";
    metric_set->hw_config_guid = "9bb6c40a-ec2c-4292-8ac8-d8b413abd301";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext193_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext193__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext193__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext193__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext193__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INPUT AVAILABLE XECORE4",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE4",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext193__rt_input_available_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE4_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE5",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE5",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext193__rt_input_available_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE5_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE6",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE6",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext193__rt_input_available_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE6_availability,
            },

            {
                .name = "RT INPUT AVAILABLE XECORE7",
                .symbol_name = "RT_INPUT_AVAILABLE_XECORE7",
                .desc = "Percentage of time in which new message is accepted by Ray Tracing Frontend",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext193__rt_input_available_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_INPUT_AVAILABLE_XECORE7_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE4",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext193__rt_traversal_step_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE5",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext193__rt_traversal_step_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE6",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext193__rt_traversal_step_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT TRAVERSAL STEP RAY COUNT XECORE7",
                .symbol_name = "RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7",
                .desc = "Number of BVH nodes processed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext193__rt_traversal_step_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext193_RT_TRAVERSAL_STEP_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext195_GPGPU_DISPATCH_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext195_GPGPU_DISPATCH_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext195_GPGPU_DISPATCH_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext195_GPGPU_DISPATCH_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext195_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext195";
    metric_set->symbol_name = "Ext195";
    metric_set->hw_config_guid = "9a911d6f-39b5-425d-aea3-15e49e6395fa";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext195_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext195__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext195__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE0",
                .symbol_name = "GPGPU_DISPATCH_XECORE0",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext195__gpgpu_dispatch_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext195_GPGPU_DISPATCH_XECORE0_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE1",
                .symbol_name = "GPGPU_DISPATCH_XECORE1",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext195__gpgpu_dispatch_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext195_GPGPU_DISPATCH_XECORE1_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE2",
                .symbol_name = "GPGPU_DISPATCH_XECORE2",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext195__gpgpu_dispatch_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext195_GPGPU_DISPATCH_XECORE2_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE3",
                .symbol_name = "GPGPU_DISPATCH_XECORE3",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext195__gpgpu_dispatch_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext195_GPGPU_DISPATCH_XECORE3_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext195__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext195__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE0 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext195__xve_multiple_pipe_active_xecore0_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE0_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE1 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext195__xve_multiple_pipe_active_xecore1_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE1_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE2 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext195__xve_multiple_pipe_active_xecore2_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE2_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE3 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext195__xve_multiple_pipe_active_xecore3_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext195_XVE_MULTIPLE_PIPE_ACTIVE_XECORE3_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext196_GPGPU_DISPATCH_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext196_GPGPU_DISPATCH_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext196_GPGPU_DISPATCH_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext196_GPGPU_DISPATCH_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext196_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext196";
    metric_set->symbol_name = "Ext196";
    metric_set->hw_config_guid = "814b3516-d465-4faa-b89c-67c30c96a256";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext196_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext196__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext196__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPGPU DISPATCH XECORE4",
                .symbol_name = "GPGPU_DISPATCH_XECORE4",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext196__gpgpu_dispatch_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext196_GPGPU_DISPATCH_XECORE4_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE5",
                .symbol_name = "GPGPU_DISPATCH_XECORE5",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext196__gpgpu_dispatch_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext196_GPGPU_DISPATCH_XECORE5_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE6",
                .symbol_name = "GPGPU_DISPATCH_XECORE6",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext196__gpgpu_dispatch_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext196_GPGPU_DISPATCH_XECORE6_availability,
            },

            {
                .name = "GPGPU DISPATCH XECORE7",
                .symbol_name = "GPGPU_DISPATCH_XECORE7",
                .desc = "Number of clocks spent dispatching GPGPU threads to XVEs",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext196__gpgpu_dispatch_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext196_GPGPU_DISPATCH_XECORE7_availability,
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext196__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext196__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE4 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext196__xve_multiple_pipe_active_xecore4_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE4_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE5 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext196__xve_multiple_pipe_active_xecore5_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE5_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE6 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext196__xve_multiple_pipe_active_xecore6_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE6_XVE0_availability,
            },

            {
                .name = "XVE MULTIPLE PIPE ACTIVE XECORE7 XVE0",
                .symbol_name = "XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0",
                .desc = "Percentage of time in which at least two pipes are actively executing a Gen ISA instruction among ALU0, ALU1 and XMX pipes",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext196__xve_multiple_pipe_active_xecore7_xve0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext196_XVE_MULTIPLE_PIPE_ACTIVE_XECORE7_XVE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext198_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext198";
    metric_set->symbol_name = "Ext198";
    metric_set->hw_config_guid = "3663ed58-377d-40c3-9af0-913cbc5d954b";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext198_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext198__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext198__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext198__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext198__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE0",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE0",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext198__slm_access_count_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE1",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE1",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext198__slm_access_count_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE2",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE2",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext198__slm_access_count_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE3",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE3",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext198__slm_access_count_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext198_SLM_ACCESS_COUNT_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext199_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext199";
    metric_set->symbol_name = "Ext199";
    metric_set->hw_config_guid = "6ce22a01-9025-4afb-b3e9-652ce0c693b5";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext199_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext199__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext199__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext199__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext199__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE0",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE0",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext199__slm_access_count_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE1",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE1",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext199__slm_access_count_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE1_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE2",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE2",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext199__slm_access_count_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE3",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE3",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext199__slm_access_count_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext199_SLM_ACCESS_COUNT_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext200_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext200";
    metric_set->symbol_name = "Ext200";
    metric_set->hw_config_guid = "7f59bef3-f0f1-4856-b4f3-e64fa9913956";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext200_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext200__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext200__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext200__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext200__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE4",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE4",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext200__slm_access_count_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE4_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE5",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE5",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext200__slm_access_count_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE5_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE6",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE6",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext200__slm_access_count_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE6_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK0 XECORE7",
                .symbol_name = "SLM_ACCESS_COUNT_BANK0_XECORE7",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext200__slm_access_count_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext200_SLM_ACCESS_COUNT_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext201_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext201";
    metric_set->symbol_name = "Ext201";
    metric_set->hw_config_guid = "8982721e-16cb-42ec-92dd-eb049ae7a503";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext201_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext201__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext201__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext201__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext201__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE4",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE4",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext201__slm_access_count_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE4_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE5",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE5",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext201__slm_access_count_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE5_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE6",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE6",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext201__slm_access_count_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE6_availability,
            },

            {
                .name = "SLM ACCESS COUNT BANK1 XECORE7",
                .symbol_name = "SLM_ACCESS_COUNT_BANK1_XECORE7",
                .desc = "Number of SLM accesses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext201__slm_access_count_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext201_SLM_ACCESS_COUNT_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}


static void
mtlgt3_add_ext202_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext202";
    metric_set->symbol_name = "Ext202";
    metric_set->hw_config_guid = "d86c1224-3af7-4df1-a44d-e4522f22b2ae";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext202_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext202__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext202__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI0",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext202__gpu_memory_l3_write_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext202__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext202__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
mtlgt3_add_ext203_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext203";
    metric_set->symbol_name = "Ext203";
    metric_set->hw_config_guid = "03090380-689d-481a-ace2-9725ea0c10d2";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext203_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext203__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext203__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 WRITE SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_WRITE_SQIDI1",
                .desc = "Number of GTI memory writes from L3 caused by L3 invalidations",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext203__gpu_memory_l3_write_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext203__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext203__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext204_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext204";
    metric_set->symbol_name = "Ext204";
    metric_set->hw_config_guid = "78a1b79a-a5fd-4fa0-b33d-2ec51404e3b9";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext204_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext204__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext204__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext204__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext204__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext204__rt_internal_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext204__rt_internal_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext204__rt_internal_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext204__rt_internal_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext204_RT_INTERNAL_NODE_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext205_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext205";
    metric_set->symbol_name = "Ext205";
    metric_set->hw_config_guid = "b3c2bff1-e203-4c90-8719-66546c370005";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext205_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext205__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext205__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext205__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext205__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE0",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext205__rt_instance_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE1",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext205__rt_instance_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE2",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext205__rt_instance_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE3",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext205__rt_instance_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext205_RT_INSTANCE_NODE_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext206_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext206";
    metric_set->symbol_name = "Ext206";
    metric_set->hw_config_guid = "a209e458-76a6-46fc-bb62-29850f38eb0d";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext206_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext206__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext206__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext206__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext206__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext206__rt_internal_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext206__rt_internal_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext206__rt_internal_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT INTERNAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INTERNAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of internal BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext206__rt_internal_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext206_RT_INTERNAL_NODE_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext207_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext207";
    metric_set->symbol_name = "Ext207";
    metric_set->hw_config_guid = "06aea283-f183-4e96-85a5-3bb7193f06c7";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext207_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext207__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext207__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext207__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext207__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE4",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext207__rt_instance_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE5",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext207__rt_instance_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE6",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext207__rt_instance_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT INSTANCE NODE RAY COUNT XECORE7",
                .symbol_name = "RT_INSTANCE_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of instance BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext207__rt_instance_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext207_RT_INSTANCE_NODE_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext212_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext212_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext212_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext212_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext212_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext212";
    metric_set->symbol_name = "Ext212";
    metric_set->hw_config_guid = "0c6d24a9-2489-4fcd-a9f6-d44380417dee";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext212_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext212__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext212__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext212__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext212__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE0",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext212__rt_procedural_node_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext212_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE1",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext212__rt_procedural_node_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext212_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE1_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE0",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE0",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext212__rt_quad_leaf_ray_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext212_RT_QUAD_LEAF_RAY_COUNT_XECORE0_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE1",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE1",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext212__rt_quad_leaf_ray_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext212_RT_QUAD_LEAF_RAY_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext213_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext213_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext213_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext213_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext213_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext213";
    metric_set->symbol_name = "Ext213";
    metric_set->hw_config_guid = "39a43efe-ee39-4fa2-88c4-3dfc34a74f4f";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext213_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext213__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext213__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext213__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext213__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE4",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext213__rt_procedural_node_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext213_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE5",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext213__rt_procedural_node_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext213_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE5_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE4",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE4",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext213__rt_quad_leaf_ray_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext213_RT_QUAD_LEAF_RAY_COUNT_XECORE4_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE5",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE5",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext213__rt_quad_leaf_ray_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext213_RT_QUAD_LEAF_RAY_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext214_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext214_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext214_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext214_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext214_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext214";
    metric_set->symbol_name = "Ext214";
    metric_set->hw_config_guid = "f3ca645b-a2b3-496b-bf6d-f8f26b1faa86";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext214_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext214__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext214__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext214__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext214__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE2",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext214__rt_procedural_node_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext214_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE3",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext214__rt_procedural_node_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext214_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE3_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE2",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE2",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext214__rt_quad_leaf_ray_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext214_RT_QUAD_LEAF_RAY_COUNT_XECORE2_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE3",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE3",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext214__rt_quad_leaf_ray_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext214_RT_QUAD_LEAF_RAY_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext215_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext215_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext215_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext215_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext215_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext215";
    metric_set->symbol_name = "Ext215";
    metric_set->hw_config_guid = "947b168e-df39-4e92-a622-0884c81221b3";
    metric_set->counters = calloc(7, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext215_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext215__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext215__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext215__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext215__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE6",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext215__rt_procedural_node_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext215_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT PROCEDURAL NODE RAY COUNT XECORE7",
                .symbol_name = "RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7",
                .desc = "Number of procedural BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext215__rt_procedural_node_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext215_RT_PROCEDURAL_NODE_RAY_COUNT_XECORE7_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE6",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE6",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext215__rt_quad_leaf_ray_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext215_RT_QUAD_LEAF_RAY_COUNT_XECORE6_availability,
            },

            {
                .name = "RT QUAD LEAF RAY COUNT XECORE7",
                .symbol_name = "RT_QUAD_LEAF_RAY_COUNT_XECORE7",
                .desc = "Number of triangle BVH nodes processed by the traversal function",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext215__rt_quad_leaf_ray_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext215_RT_QUAD_LEAF_RAY_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 7);
}

static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext220_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext220";
    metric_set->symbol_name = "Ext220";
    metric_set->hw_config_guid = "0722885e-4df8-4c98-8336-72b5e129e6be";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext220_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext220__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext220__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext220__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext220__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "RT BVH CACHE MISS XECORE0",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE0",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE0_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE1",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE1",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE1_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE2",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE2",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE2_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE3",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE3",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE3_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE4",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE4",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE4_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE5",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE5",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE5_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE6",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE6",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE6_availability,
            },

            {
                .name = "RT BVH CACHE MISS XECORE7",
                .symbol_name = "RT_BVH_CACHE_MISS_XECORE7",
                .desc = "Number of BVH cache misses for RayQuery only",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext220__rt_bvh_cache_miss_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext220_RT_BVH_CACHE_MISS_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext225_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext225_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext225";
    metric_set->symbol_name = "Ext225";
    metric_set->hw_config_guid = "db4a27f8-40a0-4cb5-aa3a-5368add92cd5";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext225_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext225__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext225__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext225__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext225__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext225__pixel_2x2_lit_post_rasterizer_early_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext225_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext226_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext226_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext226";
    metric_set->symbol_name = "Ext226";
    metric_set->hw_config_guid = "6b5736f5-a627-4cb6-9078-1c05137bc460";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext226_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext226__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext226__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext226__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext226__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER EARLY DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1",
                .desc = "Number of promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext226__pixel_2x2_lit_post_rasterizer_early_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext226_PIXEL_2x2_LIT_POST_RASTERIZER_EARLY_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext227_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext227_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext227";
    metric_set->symbol_name = "Ext227";
    metric_set->hw_config_guid = "5e6f4959-c37c-4be0-bb4e-2f1c1aef2bb3";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext227_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext227__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext227__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext227__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext227__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE0",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext227__pixel_2x2_lit_post_rasterizer_late_depth_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext227_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext228_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext228_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext228";
    metric_set->symbol_name = "Ext228";
    metric_set->hw_config_guid = "fe2d673e-8b2e-47d0-b9db-2c50e10ee53e";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext228_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext228__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext228__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext228__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext228__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL 2x2 LIT POST RASTERIZER LATE DEPTH SLICE1",
                .symbol_name = "PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1",
                .desc = "Number of non-promoted 2x2 that are lit from Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext228__pixel_2x2_lit_post_rasterizer_late_depth_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext228_PIXEL_2x2_LIT_POST_RASTERIZER_LATE_DEPTH_SLICE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext229_SLM_BANK_CONFLICT_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext229_SLM_BANK_CONFLICT_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext229_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext229";
    metric_set->symbol_name = "Ext229";
    metric_set->hw_config_guid = "cb94a696-bfbe-4566-8225-c337f988600c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext229_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext229__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext229__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext229__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext229__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE0",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE0",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext229__slm_bank_conflict_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext229_SLM_BANK_CONFLICT_COUNT_XECORE0_availability,
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE1",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE1",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext229__slm_bank_conflict_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext229_SLM_BANK_CONFLICT_COUNT_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext230_SLM_BANK_CONFLICT_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext230_SLM_BANK_CONFLICT_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext230_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext230";
    metric_set->symbol_name = "Ext230";
    metric_set->hw_config_guid = "ec3032cb-df12-445c-9eb2-6b1031d2dc86";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext230_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext230__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext230__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext230__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext230__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE4",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE4",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext230__slm_bank_conflict_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext230_SLM_BANK_CONFLICT_COUNT_XECORE4_availability,
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE5",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE5",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext230__slm_bank_conflict_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext230_SLM_BANK_CONFLICT_COUNT_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext231_SLM_BANK_CONFLICT_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext231_SLM_BANK_CONFLICT_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext231_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext231";
    metric_set->symbol_name = "Ext231";
    metric_set->hw_config_guid = "e5e22fbb-0ff4-44f6-a549-6ed41df0dd27";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext231_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext231__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext231__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext231__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext231__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE2",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE2",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext231__slm_bank_conflict_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext231_SLM_BANK_CONFLICT_COUNT_XECORE2_availability,
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE3",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE3",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext231__slm_bank_conflict_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext231_SLM_BANK_CONFLICT_COUNT_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext232_SLM_BANK_CONFLICT_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext232_SLM_BANK_CONFLICT_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext232_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext232";
    metric_set->symbol_name = "Ext232";
    metric_set->hw_config_guid = "b6defb71-0fe8-400e-ae27-565ce9067082";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext232_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext232__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext232__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext232__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext232__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE6",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE6",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext232__slm_bank_conflict_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext232_SLM_BANK_CONFLICT_COUNT_XECORE6_availability,
            },

            {
                .name = "SLM BANK CONFLICT COUNT XECORE7",
                .symbol_name = "SLM_BANK_CONFLICT_COUNT_XECORE7",
                .desc = "Number of SLM accesses resulting in a bank conflict",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext232__slm_bank_conflict_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext232_SLM_BANK_CONFLICT_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext236_L3_MISS_L3BANK0_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext236_L3_MISS_L3BANK1_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext236_L3_MISS_L3BANK2_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext236_L3_MISS_L3BANK3_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext236_L3_MISS_L3BANK4_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext236_L3_MISS_L3BANK5_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext236_L3_MISS_L3BANK6_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext236_L3_MISS_L3BANK7_availability(const struct intel_perf *perf) {
    if (perf->devinfo.slice_mask & ((3 << (0 * 2)))) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext236_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext236";
    metric_set->symbol_name = "Ext236";
    metric_set->hw_config_guid = "98d5c3d9-bca6-4699-99e3-7b95a23025ce";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext236_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext236__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext236__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext236__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext236__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "L3 MISS L3BANK0",
                .symbol_name = "L3_MISS_L3BANK0",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK0_availability,
            },

            {
                .name = "L3 MISS L3BANK1",
                .symbol_name = "L3_MISS_L3BANK1",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK1_availability,
            },

            {
                .name = "L3 MISS L3BANK2",
                .symbol_name = "L3_MISS_L3BANK2",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK2_availability,
            },

            {
                .name = "L3 MISS L3BANK3",
                .symbol_name = "L3_MISS_L3BANK3",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK3_availability,
            },

            {
                .name = "L3 MISS L3BANK4",
                .symbol_name = "L3_MISS_L3BANK4",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK4_availability,
            },

            {
                .name = "L3 MISS L3BANK5",
                .symbol_name = "L3_MISS_L3BANK5",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK5_availability,
            },

            {
                .name = "L3 MISS L3BANK6",
                .symbol_name = "L3_MISS_L3BANK6",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK6_availability,
            },

            {
                .name = "L3 MISS L3BANK7",
                .symbol_name = "L3_MISS_L3BANK7",
                .desc = "Number of L3 accesses which miss in the L3 cache",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext236__l3_miss_l3_bank7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GTI/L3",
                .availability = mtlgt3_ext236_L3_MISS_L3BANK7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}

static bool mtlgt3_ext237_AMFS_L3_WRITE_SLICE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_AMFS_L3_WRITE_SLICE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_slice_available(&perf->devinfo, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext237_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext237";
    metric_set->symbol_name = "Ext237";
    metric_set->hw_config_guid = "4256db1d-9083-4497-9000-59bbcf9eee72";
    metric_set->counters = calloc(13, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext237_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AMFS L3 WRITE SLICE0",
                .symbol_name = "AMFS_L3_WRITE_SLICE0",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__amfs_l3_write_slice0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_AMFS_L3_WRITE_SLICE0_availability,
            },

            {
                .name = "AMFS L3 WRITE SLICE1",
                .symbol_name = "AMFS_L3_WRITE_SLICE1",
                .desc = "Number of AMFS writes to L3",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__amfs_l3_write_slice1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_AMFS_L3_WRITE_SLICE1_availability,
            },

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext237__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext237__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext237__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext237__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE0",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE0_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE1",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE1_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE2",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE2_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE3",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE3_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE4",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE4_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE5",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE5_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE6",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE6_availability,
            },

            {
                .name = "XVE DATAPORT FENCE MESSAGE COUNT XECORE7",
                .symbol_name = "XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7",
                .desc = "Number of fence messages sent by XVEs to the Dataport",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext237__xve_dataport_fence_message_count_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext237_XVE_DATAPORT_FENCE_MESSAGE_COUNT_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 13);
}


static void
mtlgt3_add_ext239_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext239";
    metric_set->symbol_name = "Ext239";
    metric_set->hw_config_guid = "5ba2bf20-ca4e-4872-86fd-9026c9de8c93";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext239_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext239__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext239__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI0",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI0",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext239__gpu_memory_l3_read_sqidi0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext239__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext239__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}


static void
mtlgt3_add_ext240_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext240";
    metric_set->symbol_name = "Ext240";
    metric_set->hw_config_guid = "fe8810c2-457b-47e0-a3b9-50cab24718b4";
    metric_set->counters = calloc(4, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext240_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext240__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext240__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU MEMORY L3 READ SQIDI1",
                .symbol_name = "GPU_MEMORY_L3_READ_SQIDI1",
                .desc = "Number of GTI memory reads from L3 caused by L3 Cache misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext240__gpu_memory_l3_read_sqidi1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext240__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext240__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 4);
}

static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext500_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext500";
    metric_set->symbol_name = "Ext500";
    metric_set->hw_config_guid = "ee0cc3d0-9ac8-4608-aaca-b37fd9d18238";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext500_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext500__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext500__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext500__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext500__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK0 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK0 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_hit_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_HIT_BANK0_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK0 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK0_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext500__icache_miss_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext500_ICACHE_MISS_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext501_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext501";
    metric_set->symbol_name = "Ext501";
    metric_set->hw_config_guid = "f6e20d5b-52be-4035-85c2-818a690bf601";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext501_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext501__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext501__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext501__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext501__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK1 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK1 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_hit_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_HIT_BANK1_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK1 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK1_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext501__icache_miss_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext501_ICACHE_MISS_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext502_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext502";
    metric_set->symbol_name = "Ext502";
    metric_set->hw_config_guid = "d09cedef-e3e3-41b5-8ce8-ddc3933339ca";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext502_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext502__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext502__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext502__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext502__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK2 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK2 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_hit_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_HIT_BANK2_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK2 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK2_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext502__icache_miss_bank2_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext502_ICACHE_MISS_BANK2_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext503_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext503";
    metric_set->symbol_name = "Ext503";
    metric_set->hw_config_guid = "96067625-3663-4f9a-8b26-74e47ab1aff4";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext503_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext503__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext503__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext503__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext503__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "ICACHE HIT BANK3 XECORE0",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE1",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE2",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE3",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE4",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE5",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE6",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE HIT BANK3 XECORE7",
                .symbol_name = "ICACHE_HIT_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Hits",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_hit_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_HIT_BANK3_XECORE7_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE0",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE0",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE0_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE1",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE1",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE1_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE2",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE2",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE2_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE3",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE3",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE3_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE4",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE4",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE4_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE5",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE5",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE5_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE6",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE6",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE6_availability,
            },

            {
                .name = "ICACHE MISS BANK3 XECORE7",
                .symbol_name = "ICACHE_MISS_BANK3_XECORE7",
                .desc = "Number of Instruction Cache Misses",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext503__icache_miss_bank3_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext503_ICACHE_MISS_BANK3_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}

static bool mtlgt3_ext508_SLM_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext508_SLM_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext508_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext508";
    metric_set->symbol_name = "Ext508";
    metric_set->hw_config_guid = "2bc8b90d-997c-4d62-b101-fe1aa74036e5";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext508_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext508__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext508__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext508__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext508__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext508__slm_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext508_SLM_BYTE_READ_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext508__slm_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext508_SLM_BYTE_READ_BANK0_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext509_SLM_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext509_SLM_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext509_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext509";
    metric_set->symbol_name = "Ext509";
    metric_set->hw_config_guid = "79252877-1dcd-4700-b4bd-58bce74b796d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext509_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext509__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext509__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext509__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext509__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext509__slm_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext509_SLM_BYTE_READ_BANK1_XECORE0_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext509__slm_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext509_SLM_BYTE_READ_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext510_SLM_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext510_SLM_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext510_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext510";
    metric_set->symbol_name = "Ext510";
    metric_set->hw_config_guid = "68ac1770-b062-48cd-94f4-44c6ae16867a";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext510_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext510__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext510__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext510__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext510__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext510__slm_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext510_SLM_BYTE_READ_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext510__slm_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext510_SLM_BYTE_READ_BANK0_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext511_SLM_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext511_SLM_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext511_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext511";
    metric_set->symbol_name = "Ext511";
    metric_set->hw_config_guid = "443b8a84-7e77-4e9f-8a2a-56743897cba3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext511_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext511__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext511__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext511__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext511__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext511__slm_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext511_SLM_BYTE_READ_BANK1_XECORE2_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext511__slm_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext511_SLM_BYTE_READ_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext512_SLM_BYTE_READ_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext512_SLM_BYTE_READ_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext512_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext512";
    metric_set->symbol_name = "Ext512";
    metric_set->hw_config_guid = "68581669-8e57-4ff9-bb70-71a99f8454c8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext512_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext512__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext512__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext512__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext512__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE4",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE4",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext512__slm_byte_read_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext512_SLM_BYTE_READ_BANK0_XECORE4_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE5",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE5",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext512__slm_byte_read_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext512_SLM_BYTE_READ_BANK0_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext513_SLM_BYTE_READ_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext513_SLM_BYTE_READ_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext513_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext513";
    metric_set->symbol_name = "Ext513";
    metric_set->hw_config_guid = "1b49d31f-4d7c-4dd7-ad31-030ccb59649e";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext513_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext513__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext513__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext513__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext513__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE4",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE4",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext513__slm_byte_read_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext513_SLM_BYTE_READ_BANK1_XECORE4_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE5",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE5",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext513__slm_byte_read_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext513_SLM_BYTE_READ_BANK1_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext514_SLM_BYTE_READ_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext514_SLM_BYTE_READ_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext514_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext514";
    metric_set->symbol_name = "Ext514";
    metric_set->hw_config_guid = "1b0ce68b-c301-4d05-8659-85fad0825057";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext514_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext514__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext514__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext514__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext514__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE6",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE6",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext514__slm_byte_read_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext514_SLM_BYTE_READ_BANK0_XECORE6_availability,
            },

            {
                .name = "SLM BYTE READ BANK0 XECORE7",
                .symbol_name = "SLM_BYTE_READ_BANK0_XECORE7",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext514__slm_byte_read_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext514_SLM_BYTE_READ_BANK0_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext515_SLM_BYTE_READ_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext515_SLM_BYTE_READ_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext515_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext515";
    metric_set->symbol_name = "Ext515";
    metric_set->hw_config_guid = "fde32e67-1a87-4946-bf96-c1ff68105749";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext515_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext515__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext515__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext515__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext515__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE6",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE6",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext515__slm_byte_read_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext515_SLM_BYTE_READ_BANK1_XECORE6_availability,
            },

            {
                .name = "SLM BYTE READ BANK1 XECORE7",
                .symbol_name = "SLM_BYTE_READ_BANK1_XECORE7",
                .desc = "Number of bytes read from SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext515__slm_byte_read_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext515_SLM_BYTE_READ_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext516_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext516_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext516_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext516";
    metric_set->symbol_name = "Ext516";
    metric_set->hw_config_guid = "bf950c5b-7250-47f4-aa59-d97b22db02ff";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext516_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext516__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext516__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext516__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext516__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext516__load_store_cache_byte_read_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext516_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext516__load_store_cache_byte_read_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext516_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext517_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext517_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext517_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext517";
    metric_set->symbol_name = "Ext517";
    metric_set->hw_config_guid = "9027ff05-4348-4061-a434-0befaba7c379";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext517_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext517__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext517__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext517__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext517__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext517__load_store_cache_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext517_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE0_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE0",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext517__load_store_cache_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext517_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext518_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext518_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext518_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext518";
    metric_set->symbol_name = "Ext518";
    metric_set->hw_config_guid = "6ad0dee9-17bf-4b54-8b70-e30afcc8710b";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext518_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext518__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext518__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext518__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext518__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext518__load_store_cache_byte_read_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext518_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext518__load_store_cache_byte_read_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext518_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext519_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext519_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext519_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext519";
    metric_set->symbol_name = "Ext519";
    metric_set->hw_config_guid = "2c2ecec8-7f33-475c-9ca4-a7e89f949f58";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext519_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext519__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext519__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext519__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext519__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext519__load_store_cache_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext519_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE1_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE1",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext519__load_store_cache_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext519_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext520_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext520_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext520_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext520";
    metric_set->symbol_name = "Ext520";
    metric_set->hw_config_guid = "d866e2a8-310e-4691-9edc-f7263b8d5c07";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext520_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext520__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext520__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext520__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext520__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext520__load_store_cache_byte_read_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext520_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext520__load_store_cache_byte_read_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext520_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext521_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext521_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext521_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext521";
    metric_set->symbol_name = "Ext521";
    metric_set->hw_config_guid = "e5a95c15-d54f-4d4f-bbe2-533240392df3";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext521_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext521__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext521__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext521__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext521__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext521__load_store_cache_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext521_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE2_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE2",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext521__load_store_cache_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext521_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext522_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext522_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext522_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext522";
    metric_set->symbol_name = "Ext522";
    metric_set->hw_config_guid = "bba76095-18aa-447d-9a79-00461a06f233";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext522_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext522__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext522__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext522__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext522__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext522__load_store_cache_byte_read_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext522_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext522__load_store_cache_byte_read_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext522_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext523_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext523_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext523_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext523";
    metric_set->symbol_name = "Ext523";
    metric_set->hw_config_guid = "724a5073-2463-4f7f-aecb-7cdd90c831e1";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext523_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext523__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext523__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext523__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext523__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext523__load_store_cache_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext523_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE3_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE3",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext523__load_store_cache_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext523_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext524_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext524_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext524_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext524";
    metric_set->symbol_name = "Ext524";
    metric_set->hw_config_guid = "3b94a07f-e4d8-4cf2-969e-ea19bb253a8c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext524_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext524__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext524__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext524__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext524__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext524__load_store_cache_byte_read_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext524_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext524__load_store_cache_byte_read_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext524_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext525_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext525_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext525_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext525";
    metric_set->symbol_name = "Ext525";
    metric_set->hw_config_guid = "f4399df4-e808-4a0a-85ff-0c66f9c9e8a4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext525_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext525__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext525__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext525__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext525__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext525__load_store_cache_byte_write_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext525_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE4_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE4",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext525__load_store_cache_byte_write_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext525_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext526_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext526_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext526_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext526";
    metric_set->symbol_name = "Ext526";
    metric_set->hw_config_guid = "f588aa78-c29a-4187-9818-480b12d5b076";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext526_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext526__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext526__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext526__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext526__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext526__load_store_cache_byte_read_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext526_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext526__load_store_cache_byte_read_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext526_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext527_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext527_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext527_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext527";
    metric_set->symbol_name = "Ext527";
    metric_set->hw_config_guid = "c0a38cc9-f0e9-40f5-9c1e-a4d7eba30825";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext527_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext527__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext527__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext527__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext527__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext527__load_store_cache_byte_write_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext527_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE5_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE5",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext527__load_store_cache_byte_write_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext527_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext528_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext528_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext528_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext528";
    metric_set->symbol_name = "Ext528";
    metric_set->hw_config_guid = "1cb1d3ff-ff5d-4c9b-84c9-89b9d235be36";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext528_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext528__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext528__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext528__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext528__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext528__load_store_cache_byte_read_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext528_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext528__load_store_cache_byte_read_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext528_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext529_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext529_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext529_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext529";
    metric_set->symbol_name = "Ext529";
    metric_set->hw_config_guid = "4491913e-99ed-4420-9575-75ab7a82c45d";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext529_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext529__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext529__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext529__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext529__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext529__load_store_cache_byte_write_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext529_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE6_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE6",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext529__load_store_cache_byte_write_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext529_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext530_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext530_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext530_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext530";
    metric_set->symbol_name = "Ext530";
    metric_set->hw_config_guid = "4fe2fe09-1ef2-45ff-87f5-e789f8405713";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext530_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext530__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext530__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext530__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext530__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK0 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext530__load_store_cache_byte_read_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext530_LOAD_STORE_CACHE_BYTE_READ_BANK0_XECORE7_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE READ BANK1 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7",
                .desc = "Number of bytes read out of the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext530__load_store_cache_byte_read_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext530_LOAD_STORE_CACHE_BYTE_READ_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext531_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext531_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext531_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext531";
    metric_set->symbol_name = "Ext531";
    metric_set->hw_config_guid = "856f213d-954d-4b0a-be6c-307b41d39b18";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext531_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext531__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext531__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext531__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext531__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK0 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext531__load_store_cache_byte_write_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext531_LOAD_STORE_CACHE_BYTE_WRITE_BANK0_XECORE7_availability,
            },

            {
                .name = "LOAD STORE CACHE BYTE WRITE BANK1 XECORE7",
                .symbol_name = "LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7",
                .desc = "Number of bytes written to the Load Store Cache, excluding THREAD_DISPATCH_QUEUE1_ACTIVE_CYCLES",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext531__load_store_cache_byte_write_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext531_LOAD_STORE_CACHE_BYTE_WRITE_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext540_SLM_BYTE_WRITE_BANK0_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext540_SLM_BYTE_WRITE_BANK1_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext540_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext540";
    metric_set->symbol_name = "Ext540";
    metric_set->hw_config_guid = "03eb9c9b-72ee-4c7b-930b-6211dbb60503";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext540_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext540__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext540__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext540__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext540__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext540__slm_byte_write_bank0_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext540_SLM_BYTE_WRITE_BANK0_XECORE0_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE0",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE0",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext540__slm_byte_write_bank1_xecore0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext540_SLM_BYTE_WRITE_BANK1_XECORE0_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext541_SLM_BYTE_WRITE_BANK0_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext541_SLM_BYTE_WRITE_BANK1_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext541_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext541";
    metric_set->symbol_name = "Ext541";
    metric_set->hw_config_guid = "e3bef1e9-f563-4927-9ce8-1be6e151448c";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext541_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext541__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext541__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext541__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext541__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext541__slm_byte_write_bank0_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext541_SLM_BYTE_WRITE_BANK0_XECORE1_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE1",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE1",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext541__slm_byte_write_bank1_xecore1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext541_SLM_BYTE_WRITE_BANK1_XECORE1_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext542_SLM_BYTE_WRITE_BANK0_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext542_SLM_BYTE_WRITE_BANK1_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext542_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext542";
    metric_set->symbol_name = "Ext542";
    metric_set->hw_config_guid = "de587fdf-1740-4816-a5c0-08c1cb6b43eb";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext542_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext542__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext542__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext542__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext542__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext542__slm_byte_write_bank0_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext542_SLM_BYTE_WRITE_BANK0_XECORE2_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE2",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE2",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext542__slm_byte_write_bank1_xecore2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext542_SLM_BYTE_WRITE_BANK1_XECORE2_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext543_SLM_BYTE_WRITE_BANK0_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext543_SLM_BYTE_WRITE_BANK1_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext543_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext543";
    metric_set->symbol_name = "Ext543";
    metric_set->hw_config_guid = "cea536f3-f7ef-449c-91fe-42c721e54b52";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext543_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext543__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext543__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext543__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext543__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext543__slm_byte_write_bank0_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext543_SLM_BYTE_WRITE_BANK0_XECORE3_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE3",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE3",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext543__slm_byte_write_bank1_xecore3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext543_SLM_BYTE_WRITE_BANK1_XECORE3_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext544_SLM_BYTE_WRITE_BANK0_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext544_SLM_BYTE_WRITE_BANK1_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext544_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext544";
    metric_set->symbol_name = "Ext544";
    metric_set->hw_config_guid = "c3586bbc-f20b-4ffc-bd62-21ea68c161f4";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext544_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext544__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext544__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext544__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext544__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE4",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE4",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext544__slm_byte_write_bank0_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext544_SLM_BYTE_WRITE_BANK0_XECORE4_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE4",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE4",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext544__slm_byte_write_bank1_xecore4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext544_SLM_BYTE_WRITE_BANK1_XECORE4_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext545_SLM_BYTE_WRITE_BANK0_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext545_SLM_BYTE_WRITE_BANK1_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext545_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext545";
    metric_set->symbol_name = "Ext545";
    metric_set->hw_config_guid = "f3d6345a-b760-4433-844e-e35204b44e09";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext545_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext545__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext545__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext545__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext545__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE5",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE5",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext545__slm_byte_write_bank0_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext545_SLM_BYTE_WRITE_BANK0_XECORE5_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE5",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE5",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext545__slm_byte_write_bank1_xecore5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext545_SLM_BYTE_WRITE_BANK1_XECORE5_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext546_SLM_BYTE_WRITE_BANK0_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext546_SLM_BYTE_WRITE_BANK1_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext546_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext546";
    metric_set->symbol_name = "Ext546";
    metric_set->hw_config_guid = "f5448b6d-cb2a-4aad-804e-b1a285299582";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext546_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext546__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext546__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext546__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext546__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE6",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE6",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext546__slm_byte_write_bank0_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext546_SLM_BYTE_WRITE_BANK0_XECORE6_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE6",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE6",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext546__slm_byte_write_bank1_xecore6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext546_SLM_BYTE_WRITE_BANK1_XECORE6_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext547_SLM_BYTE_WRITE_BANK0_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext547_SLM_BYTE_WRITE_BANK1_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext547_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext547";
    metric_set->symbol_name = "Ext547";
    metric_set->hw_config_guid = "7b8b6c53-abff-4570-b413-91cc843181d8";
    metric_set->counters = calloc(5, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext547_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext547__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext547__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext547__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext547__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "SLM BYTE WRITE BANK0 XECORE7",
                .symbol_name = "SLM_BYTE_WRITE_BANK0_XECORE7",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext547__slm_byte_write_bank0_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext547_SLM_BYTE_WRITE_BANK0_XECORE7_availability,
            },

            {
                .name = "SLM BYTE WRITE BANK1 XECORE7",
                .symbol_name = "SLM_BYTE_WRITE_BANK1_XECORE7",
                .desc = "Number of bytes written to SLM",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_THROUGHPUT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_BYTES,
                .read_uint64 = mtlgt3__ext547__slm_byte_write_bank1_xecore7__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
                .availability = mtlgt3_ext547_SLM_BYTE_WRITE_BANK1_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 5);
}

static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE0_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE1_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE2_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE3_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 0, 3)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE4_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 0)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE5_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 1)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE6_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 2)) {
        return true;
    }
    return false;
}
static bool mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE7_availability(const struct intel_perf *perf) {
    if (intel_perf_devinfo_subslice_available(&perf->devinfo, 1, 3)) {
        return true;
    }
    return false;
}

static void
mtlgt3_add_ext604_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext604";
    metric_set->symbol_name = "Ext604";
    metric_set->hw_config_guid = "b83befed-d2db-4806-907c-3f952798e117";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext604_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext604__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext604__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext604__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext604__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE0",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE1",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE2",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE3",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE4",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE5",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE6",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE0 ACTIVE CYCLES XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE7",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue0_active_cycles_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE0_ACTIVE_CYCLES_XECORE7_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE0",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE0",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore0__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE0_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE1",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE1",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore1__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE1_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE2",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE2",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore2__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE2_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE3",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE3",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore3__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE3_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE4",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE4",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore4__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE4_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE5",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE5",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore5__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE5_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE6",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE6",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore6__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE6_availability,
            },

            {
                .name = "THREADGROUP DISPATCH QUEUE1 ACTIVE CYCLES XECORE7",
                .symbol_name = "THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE7",
                .desc = "Percentage of time in which non PS thread is ready for dispatch on thread dispatcher",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext604__threadgroup_dispatch_queue1_active_cycles_xecore7__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
                .availability = mtlgt3_ext604_THREADGROUP_DISPATCH_QUEUE1_ACTIVE_CYCLES_XECORE7_availability,
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
mtlgt3_add_ext1000_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1000";
    metric_set->symbol_name = "Ext1000";
    metric_set->hw_config_guid = "0d368afb-b8fd-425d-a704-9a45eaaaed3d";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1000_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1000__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1000__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1000__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1000__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE ACTIVE CYCLES",
                .symbol_name = "XVE_ACTIVE_CYCLES",
                .desc = "Number of cycles at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_active_cycles__read,
                .max_uint64 = mtlgt3__ext1000__xve_active_cycles__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_inst_executed_alu0_all__read,
                .max_uint64 = mtlgt3__ext1000__xve_inst_executed_alu0_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_inst_executed_alu1_all__read,
                .max_uint64 = mtlgt3__ext1000__xve_inst_executed_alu1_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL",
                .desc = "Number of instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_inst_executed_control_all__read,
                .max_uint64 = mtlgt3__ext1000__xve_inst_executed_control_all__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED CONTROL ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_CONTROL_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on Jump Pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_inst_executed_control_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_inst_executed_send_all__read,
                .max_uint64 = mtlgt3__ext1000__xve_inst_executed_send_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_inst_executed_xmx_all__read,
                .max_uint64 = mtlgt3__ext1000__xve_inst_executed_xmx_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE",
                .desc = "Percentage of time in which ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE PIPE ALU0 AND ALU1 ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_ALU1_ACTIVE_CYCLES",
                .desc = "Number of cycles in ALU0 and ALU1 pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__read,
                .max_uint64 = mtlgt3__ext1000__xve_pipe_alu0_and_alu1_active_cycles__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE",
                .desc = "Percentage of time in which ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE PIPE ALU0 AND XMX ACTIVE CYCLES",
                .symbol_name = "XVE_PIPE_ALU0_AND_XMX_ACTIVE_CYCLES",
                .desc = "Number of cycles ALU0 and XMX pipes are both actively executing a Gen ISA instruction",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__read,
                .max_uint64 = mtlgt3__ext1000__xve_pipe_alu0_and_xmx_active_cycles__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_stall_cycles__read,
                .max_uint64 = mtlgt3__ext1000__xve_stall_cycles__max,
                .group = "EU Array",
            },

            {
                .name = "XVE THREADS OCCUPANCY ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_ALL",
                .desc = "Percentage of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1000__xve_threads_occupancy_all__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE THREADS OCCUPANCY CYCLES ALL",
                .symbol_name = "XVE_THREADS_OCCUPANCY_CYCLES_ALL",
                .desc = "Number of thread slots occupied",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1000__xve_threads_occupancy_cycles_all__read,
                .max_uint64 = mtlgt3__ext1000__xve_threads_occupancy_cycles_all__max,
                .group = "EU Array",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
mtlgt3_add_ext1001_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1001";
    metric_set->symbol_name = "Ext1001";
    metric_set->hw_config_guid = "08bee982-b34c-49c1-bf0c-93c1949ffbe7";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1001_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1001__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1001__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1001__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1001__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_async_cs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_async_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu0_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_cs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu0_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_ds__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_ds__max,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu0_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_hs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_hs__max,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu0_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_ps__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_ps__max,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu0_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_vs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu0_vs__max,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu0_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS",
                .desc = "Number of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_async_cs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_async_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Async Compute Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu1_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS",
                .desc = "Number of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_cs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_CS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Compute Shader (from Render Engine) on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu1_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS",
                .desc = "Number of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_ds__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_ds__max,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_DS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Domain Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu1_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS",
                .desc = "Number of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_hs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_hs__max,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_HS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Hull Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu1_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS",
                .desc = "Number of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_ps__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_ps__max,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_PS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Fragment Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu1_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS",
                .desc = "Number of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_vs__read,
                .max_uint64 = mtlgt3__ext1001__xve_inst_executed_alu1_vs__max,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_VS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Vertex Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1001__xve_inst_executed_alu1_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
mtlgt3_add_ext1002_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1002";
    metric_set->symbol_name = "Ext1002";
    metric_set->hw_config_guid = "845617a9-5a17-4f1f-9a6f-61ff844065e4";
    metric_set->counters = calloc(21, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1002_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1002__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1002__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1002__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1002__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_alu0_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_alu0_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_alu0_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_AHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Any Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_alu1_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS",
                .desc = "Number of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_CHS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Closest Hit Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_alu1_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS",
                .desc = "Number of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_RT_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by BTD Miss Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_alu1_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS",
                .desc = "Number of instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_send_rt_ahs__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_send_rt_ahs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND RT AHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_AHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Any Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_send_rt_ahs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS",
                .desc = "Number of instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_send_rt_chs__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_send_rt_chs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND RT CHS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_CHS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Closest Hit Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_send_rt_chs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS",
                .desc = "Number of instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1002__xve_inst_executed_send_rt_ms__read,
                .max_uint64 = mtlgt3__ext1002__xve_inst_executed_send_rt_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND RT MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_RT_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by BTD Miss Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1002__xve_inst_executed_send_rt_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 21);
}


static void
mtlgt3_add_ext1003_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1003";
    metric_set->symbol_name = "Ext1003";
    metric_set->hw_config_guid = "24e3b1a8-b80e-4c8c-ab21-83640d78f896";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1003_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1003__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1003__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1003__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1003__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE ACTIVE",
                .symbol_name = "XVE_ACTIVE",
                .desc = "Percentage of time in which at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE ACTIVE ASYNC CS",
                .symbol_name = "XVE_ACTIVE_ASYNC_CS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Async Compute Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_async_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE CS",
                .symbol_name = "XVE_ACTIVE_CS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Compute Shader (from Render Engine) threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES",
                .symbol_name = "XVE_ACTIVE_CYCLES",
                .desc = "Number of cycles at least one pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles__max,
                .group = "EU Array",
            },

            {
                .name = "XVE ACTIVE CYCLES ASYNC CS",
                .symbol_name = "XVE_ACTIVE_CYCLES_ASYNC_CS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Async Compute Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_async_cs__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_async_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES CS",
                .symbol_name = "XVE_ACTIVE_CYCLES_CS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Compute Shader (from Render Engine) threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_cs__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES DS",
                .symbol_name = "XVE_ACTIVE_CYCLES_DS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Domain Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_ds__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_ds__max,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES HS",
                .symbol_name = "XVE_ACTIVE_CYCLES_HS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Hull Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_hs__read,
                .max_uint64 = percentage_max_callback_uint64,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES MS",
                .symbol_name = "XVE_ACTIVE_CYCLES_MS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Mesh Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_ms__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES FS",
                .symbol_name = "XVE_ACTIVE_CYCLES_PS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Fragment Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_ps__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_ps__max,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES RT",
                .symbol_name = "XVE_ACTIVE_CYCLES_RT",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Ray Tracing Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_rt__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_rt__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES TS",
                .symbol_name = "XVE_ACTIVE_CYCLES_TS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Task Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_ts__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_ts__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE CYCLES VS",
                .symbol_name = "XVE_ACTIVE_CYCLES_VS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Vertex Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1003__xve_active_cycles_vs__read,
                .max_uint64 = mtlgt3__ext1003__xve_active_cycles_vs__max,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE ACTIVE DS",
                .symbol_name = "XVE_ACTIVE_DS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Domain Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_ds__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE ACTIVE HS",
                .symbol_name = "XVE_ACTIVE_HS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Hull Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_hs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE ACTIVE MS",
                .symbol_name = "XVE_ACTIVE_MS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Mesh Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_ms__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE FS",
                .symbol_name = "XVE_ACTIVE_PS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Fragment Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_ps__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE ACTIVE RT",
                .symbol_name = "XVE_ACTIVE_RT",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Ray Tracing Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_rt__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE TS",
                .symbol_name = "XVE_ACTIVE_TS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Task Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_ts__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE ACTIVE VS",
                .symbol_name = "XVE_ACTIVE_VS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Vertex Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1003__xve_active_vs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
mtlgt3_add_ext1004_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1004";
    metric_set->symbol_name = "Ext1004";
    metric_set->hw_config_guid = "974d6469-d51f-4e4a-a393-32033f9b562e";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1004_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1004__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1004__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1004__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1004__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE STALL",
                .symbol_name = "XVE_STALL",
                .desc = "Percentage of time in which any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE STALL ASYNC CS",
                .symbol_name = "XVE_STALL_ASYNC_CS",
                .desc = "Percentage of time in which there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_async_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CS",
                .symbol_name = "XVE_STALL_CS",
                .desc = "Percentage of time in which there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_cs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CYCLES",
                .symbol_name = "XVE_STALL_CYCLES",
                .desc = "Number of cycles any threads are loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles__max,
                .group = "EU Array",
            },

            {
                .name = "XVE STALL CYCLES ASYNC CS",
                .symbol_name = "XVE_STALL_CYCLES_ASYNC_CS",
                .desc = "Number of cycles there are Async Compute Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_async_cs__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_async_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CYCLES CS",
                .symbol_name = "XVE_STALL_CYCLES_CS",
                .desc = "Number of cycles there are Compute Shader (from Render Engine) threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_cs__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CYCLES DS",
                .symbol_name = "XVE_STALL_CYCLES_DS",
                .desc = "Number of cycles there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_ds__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_ds__max,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE STALL CYCLES HS",
                .symbol_name = "XVE_STALL_CYCLES_HS",
                .desc = "Number of cycles there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_hs__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_hs__max,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE STALL CYCLES MS",
                .symbol_name = "XVE_STALL_CYCLES_MS",
                .desc = "Number of cycles there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_ms__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CYCLES FS",
                .symbol_name = "XVE_STALL_CYCLES_PS",
                .desc = "Number of cycles there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_ps__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_ps__max,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE STALL CYCLES RT",
                .symbol_name = "XVE_STALL_CYCLES_RT",
                .desc = "Number of cycles there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_rt__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_rt__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CYCLES TS",
                .symbol_name = "XVE_STALL_CYCLES_TS",
                .desc = "Number of cycles there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_ts__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_ts__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CYCLES VS",
                .symbol_name = "XVE_STALL_CYCLES_VS",
                .desc = "Number of cycles there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1004__xve_stall_cycles_vs__read,
                .max_uint64 = mtlgt3__ext1004__xve_stall_cycles_vs__max,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE STALL DS",
                .symbol_name = "XVE_STALL_DS",
                .desc = "Percentage of time in which there are Domain Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_ds__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE STALL HS",
                .symbol_name = "XVE_STALL_HS",
                .desc = "Percentage of time in which there are Hull Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_hs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE STALL MS",
                .symbol_name = "XVE_STALL_MS",
                .desc = "Percentage of time in which there are Mesh Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_ms__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL FS",
                .symbol_name = "XVE_STALL_PS",
                .desc = "Percentage of time in which there are Fragment Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_ps__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE STALL RT",
                .symbol_name = "XVE_STALL_RT",
                .desc = "Percentage of time in which there are Ray Tracing Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_rt__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL TS",
                .symbol_name = "XVE_STALL_TS",
                .desc = "Percentage of time in which there are Task Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_ts__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL VS",
                .symbol_name = "XVE_STALL_VS",
                .desc = "Percentage of time in which there are Vertex Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1004__xve_stall_vs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
mtlgt3_add_ext1005_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1005";
    metric_set->symbol_name = "Ext1005";
    metric_set->hw_config_guid = "c172fb87-e53f-468d-893a-d8528684accc";
    metric_set->counters = calloc(27, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1005_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1005__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1005__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1005__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1005__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_alu0_all__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_alu0_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED ALU0 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_alu0_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL",
                .desc = "Number of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_alu1_all__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_alu1_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED ALU1 ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_alu1_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED FP16",
                .symbol_name = "XVE_INST_EXECUTED_FP16",
                .desc = "Number of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_fp16__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_fp16__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED FP32",
                .symbol_name = "XVE_INST_EXECUTED_FP32",
                .desc = "Number of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_fp32__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_fp32__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED FP32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP32_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_fp32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED FP64",
                .symbol_name = "XVE_INST_EXECUTED_FP64",
                .desc = "The number of FLT64 instructions executed in ALU0 INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_fp64__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_fp64__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED FP64 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_FP64_UTILIZATION",
                .desc = "The percentage of time in which FLT64 instruction were processed actively on FPU INT64 pipeline.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_fp64_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED INT16",
                .symbol_name = "XVE_INST_EXECUTED_INT16",
                .desc = "Number of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_int16__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_int16__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED INT16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT16_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT16 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_int16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED INT32",
                .symbol_name = "XVE_INST_EXECUTED_INT32",
                .desc = "Number of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_int32__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_int32__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED INT32 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_INT32_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT32 ALU instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_int32_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED MATH",
                .symbol_name = "XVE_INST_EXECUTED_MATH",
                .desc = "Number of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_math__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_math__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED MATH UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_MATH_UTILIZATION",
                .desc = "Percentage of execution slots taken by extended math instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_math_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL",
                .desc = "Number of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_all__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED XMX ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_ALL_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed in XMX pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_xmx_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16",
                .desc = "Number of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_bf16__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_bf16__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED XMX BF16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_BF16_UTILIZATION",
                .desc = "Percentage of execution slots taken by BF16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_xmx_bf16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16",
                .desc = "Number of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_fp16__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_fp16__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED XMX FP16 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_FP16_UTILIZATION",
                .desc = "Percentage of execution slots taken by FP16 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_xmx_fp16_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8",
                .desc = "Number of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_int8__read,
                .max_uint64 = mtlgt3__ext1005__xve_inst_executed_xmx_int8__max,
                .group = "EU Array",
            },

            {
                .name = "XVE INST EXECUTED XMX INT8 UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_XMX_INT8_UTILIZATION",
                .desc = "Percentage of execution slots taken by INT8 XMX instructions",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1005__xve_inst_executed_xmx_int8_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 27);
}


static void
mtlgt3_add_ext1006_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1006";
    metric_set->symbol_name = "Ext1006";
    metric_set->hw_config_guid = "f739508f-51b2-48df-839c-e92c14d14c64";
    metric_set->counters = calloc(23, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1006_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1006__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1006__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1006__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1006__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL",
                .desc = "Number of instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_all__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_all__max,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED SEND ALL UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ALL_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_all_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Pipes",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS",
                .desc = "Number of instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_async_cs__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_async_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND ASYNC CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_ASYNC_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Async Compute Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_async_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND CS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS",
                .desc = "Number of instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_cs__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_cs__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND CS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_CS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Compute Shader (from Render Engine) threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_cs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND DS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS",
                .desc = "Number of instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ds__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ds__max,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND DS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_DS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Domain Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_ds_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Domain Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND GS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS",
                .desc = "Number of instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_gs__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_gs__max,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_GS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Geometry Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND HS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS",
                .desc = "Number of instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_hs__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_hs__max,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND HS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_HS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Hull Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_hs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Hull Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND MS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS",
                .desc = "Number of instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ms__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_MS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Mesh Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND FS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS",
                .desc = "Number of instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ps__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ps__max,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND FS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_PS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Fragment Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_ps_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Fragment Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND TS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS",
                .desc = "Number of instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ts__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_ts__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_TS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Task Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND VS",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS",
                .desc = "Number of instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1006__xve_inst_executed_send_vs__read,
                .max_uint64 = mtlgt3__ext1006__xve_inst_executed_send_vs__max,
                .group = "EU Array/Vertex Shader",
            },

            {
                .name = "XVE INST EXECUTED SEND VS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_SEND_VS_UTILIZATION",
                .desc = "Percentage of time taken by instructions executed by Vertex Shader threads on SEND pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1006__xve_inst_executed_send_vs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Vertex Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 23);
}


static void
mtlgt3_add_ext1007_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1007";
    metric_set->symbol_name = "Ext1007";
    metric_set->hw_config_guid = "926b1773-807e-4ee5-8561-30c9eb0a6344";
    metric_set->counters = calloc(19, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1007_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1007__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1007__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1007__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1007__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "XVE ACTIVE CYCLES GS",
                .symbol_name = "XVE_ACTIVE_CYCLES_GS",
                .desc = "Number of cycles at least one pipe is active in XVE and there are Geometry Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_active_cycles_gs__read,
                .max_uint64 = mtlgt3__ext1007__xve_active_cycles_gs__max,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE ACTIVE GS",
                .symbol_name = "XVE_ACTIVE_GS",
                .desc = "Percentage of time in which at least one pipe is active in XVE and there are Geometry Shader threads loaded",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_active_gs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_inst_executed_alu0_gs__read,
                .max_uint64 = mtlgt3__ext1007__xve_inst_executed_alu0_gs__max,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_inst_executed_alu0_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_inst_executed_alu0_ms__read,
                .max_uint64 = mtlgt3__ext1007__xve_inst_executed_alu0_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_inst_executed_alu0_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_inst_executed_alu0_ts__read,
                .max_uint64 = mtlgt3__ext1007__xve_inst_executed_alu0_ts__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU0 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU0_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU0 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_inst_executed_alu0_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS",
                .desc = "Number of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_inst_executed_alu1_gs__read,
                .max_uint64 = mtlgt3__ext1007__xve_inst_executed_alu1_gs__max,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 GS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_GS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Geometry Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_inst_executed_alu1_gs_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS",
                .desc = "Number of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_inst_executed_alu1_ms__read,
                .max_uint64 = mtlgt3__ext1007__xve_inst_executed_alu1_ms__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 MS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_MS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Mesh Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_inst_executed_alu1_ms_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS",
                .desc = "Number of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_inst_executed_alu1_ts__read,
                .max_uint64 = mtlgt3__ext1007__xve_inst_executed_alu1_ts__max,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE INST EXECUTED ALU1 TS UTILIZATION",
                .symbol_name = "XVE_INST_EXECUTED_ALU1_TS_UTILIZATION",
                .desc = "Percentage of execution slots taken by instructions executed by Task Shader on ALU1 pipe",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_inst_executed_alu1_ts_utilization__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Compute Shader",
            },

            {
                .name = "XVE STALL CYCLES GS",
                .symbol_name = "XVE_STALL_CYCLES_GS",
                .desc = "Number of cycles there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__ext1007__xve_stall_cycles_gs__read,
                .max_uint64 = mtlgt3__ext1007__xve_stall_cycles_gs__max,
                .group = "EU Array/Geometry Shader",
            },

            {
                .name = "XVE STALL GS",
                .symbol_name = "XVE_STALL_GS",
                .desc = "Percentage of time in which there are Geometry Shader threads loaded but not even a single pipe is active in XVE",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__ext1007__xve_stall_gs__read,
                .max_float = percentage_max_callback_float,
                .group = "EU Array/Geometry Shader",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 19);
}


static void
mtlgt3_add_ext1010_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "Ext1010";
    metric_set->symbol_name = "Ext1010";
    metric_set->hw_config_guid = "82f69b49-772a-4169-bf9a-b1ef08e0823b";
    metric_set->counters = calloc(8, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OA_FORMAT_A24u40_A14u32_B8_C8;

    metric_set->perf_raw_size = 256;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 38;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_ext1010_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__ext1010__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__ext1010__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__ext1010__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "Time elapsed on the GPU during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__ext1010__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "PIXEL BLEND",
                .symbol_name = "PIXEL_BLEND",
                .desc = "Number of blended 2x2 pixels written to all render targets",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__ext1010__pixel_blend__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "PIXEL WRITE",
                .symbol_name = "PIXEL_WRITE",
                .desc = "Number of 2x2 pixels written to all render targets",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__ext1010__pixel_write__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "POSTPS DEPTH STENCIL ALPHA TEST FAIL",
                .symbol_name = "POSTPS_DEPTH_STENCIL_ALPHA_TEST_FAIL",
                .desc = "Number of 2x2 that were lit from Rasterizer but failed the depth stencil test or alpha test",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__ext1010__postps_depth_stencil_alpha_test_fail__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Output Merger",
            },

            {
                .name = "RASTERIZER SAMPLE OUTPUT",
                .symbol_name = "RASTERIZER_SAMPLE_OUTPUT",
                .desc = "Number of lit samples emitted by Rasterizer",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PIXELS,
                .read_uint64 = mtlgt3__ext1010__rasterizer_sample_output__read,
                .max_uint64 = NULL /* undefined */,
                .group = "3D Pipe/Rasterizer",
            },

            {
                .name = "SAMPLER 2X2 READ",
                .symbol_name = "SAMPLER_2X2_READ",
                .desc = "Number of 2x2 texel block requested from Sampler",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_TEXELS,
                .read_uint64 = mtlgt3__ext1010__sampler_2_x2_read__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Sampler/Sampler Input",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 8);
}


static void
mtlgt3_add_media_set1_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "MediaSet1";
    metric_set->symbol_name = "MediaSet1";
    metric_set->hw_config_guid = "4d9b2817-19b9-4461-a54b-dc9fdb7d69cb";
    metric_set->counters = calloc(11, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OAM_FORMAT_MPEC8u32_B8_C8;

    metric_set->perf_raw_size = 128;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 8;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_media_set1_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__media_set1__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__media_set1__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__media_set1__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "GPU Time Elapsed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__media_set1__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX0_READ_REQUEST",
                .symbol_name = "VIDEO_DECODE_BOX0_READ_REQUEST",
                .desc = "Number of VDBOX0 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_decode_box0_read_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX0_WRITE_REQUEST",
                .symbol_name = "VIDEO_DECODE_BOX0_WRITE_REQUEST",
                .desc = "Number of VDBOX0 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_decode_box0_write_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX1_READ_REQUEST",
                .symbol_name = "VIDEO_DECODE_BOX1_READ_REQUEST",
                .desc = "Number of VDBOX1 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_decode_box1_read_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX1_WRITE_REQUEST",
                .symbol_name = "VIDEO_DECODE_BOX1_WRITE_REQUEST",
                .desc = "Number of VDBOX1 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_decode_box1_write_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_ENHANCEMENT_BOX0_READ_REQUEST",
                .symbol_name = "VIDEO_ENHANCEMENT_BOX0_READ_REQUEST",
                .desc = "Number of VEBOX0 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_enhancement_box0_read_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_ENHANCEMENT_BOX0_WRITE_REQUEST",
                .symbol_name = "VIDEO_ENHANCEMENT_BOX0_WRITE_REQUEST",
                .desc = "Number of VEBOX0 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_enhancement_box0_write_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_ENHANCEMENT_BOX1_READ_REQUEST",
                .symbol_name = "VIDEO_ENHANCEMENT_BOX1_READ_REQUEST",
                .desc = "Number of VEBOX1 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_enhancement_box1_read_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_ENHANCEMENT_BOX1_WRITE_REQUEST",
                .symbol_name = "VIDEO_ENHANCEMENT_BOX1_WRITE_REQUEST",
                .desc = "Number of VEBOX1 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set1__video_enhancement_box1_write_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 11);
}


static void
mtlgt3_add_media_set2_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "MediaSet2";
    metric_set->symbol_name = "MediaSet2";
    metric_set->hw_config_guid = "651a6694-0ac1-4bd5-a4a1-94bcf479d4f4";
    metric_set->counters = calloc(10, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OAM_FORMAT_MPEC8u32_B8_C8;

    metric_set->perf_raw_size = 128;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 8;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_media_set2_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__media_set2__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__media_set2__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "COMMAND_PARSER_GRAPHICS_SECURITY_CONTROLLER_BUSY",
                .symbol_name = "COMMAND_PARSER_GRAPHICS_SECURITY_CONTROLLER_BUSY",
                .desc = "Percentage of time in which Graphics Security Controller is active.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__media_set2__command_parser_graphics_security_controller_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "COMMAND PARSER VIDEO DECODE_ENGINE0 BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_DECODE_ENGINE0_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the media VDBOX0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__media_set2__command_parser_video_decode_engine0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "COMMAND_PARSER_VIDEO_DECODE_ENGINE1_BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_DECODE_ENGINE1_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the media VDBOX1",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__media_set2__command_parser_video_decode_engine1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE0_BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE0_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the media VEBOX0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__media_set2__command_parser_video_enhancement_engine0_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE1_BUSY",
                .symbol_name = "COMMAND_PARSER_VIDEO_ENHANCEMENT_ENGINE1_BUSY",
                .desc = "Percentage of time in which there is a context loaded and active on the media VEBOX0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_RAW,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_FLOAT,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_PERCENT,
                .read_float = mtlgt3__media_set2__command_parser_video_enhancement_engine1_busy__read,
                .max_float = percentage_max_callback_float,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__media_set2__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "GPU Time Elapsed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__media_set2__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "MEDIA_READ_REQUEST",
                .symbol_name = "MEDIA_READ_REQUEST",
                .desc = "Number of read requests from stand alone media ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set2__media_read_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "MEDIA_WRITE_REQUEST",
                .symbol_name = "MEDIA_WRITE_REQUEST",
                .desc = "Number of write requests from stand alone media ",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__media_set2__media_write_request__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 10);
}


static void
mtlgt3_add_test_oam_metric_set(struct intel_perf *perf)
{
    struct intel_perf_metric_set *metric_set;
    struct intel_perf_logical_counter *counter;

    metric_set = calloc(1, sizeof(*metric_set));
    metric_set->name = "TestOam";
    metric_set->symbol_name = "TestOam";
    metric_set->hw_config_guid = "bac01106-5869-489c-a306-67303a434173";
    metric_set->counters = calloc(15, sizeof(struct intel_perf_logical_counter));
    metric_set->n_counters = 0;
    metric_set->perf_oa_metrics_set = 0; // determined at runtime
    metric_set->perf_oa_format = I915_OAM_FORMAT_MPEC8u32_B8_C8;

    metric_set->perf_raw_size = 128;
    metric_set->gpu_time_offset = 0;
    metric_set->gpu_clock_offset = 1;
    metric_set->a_offset = 2;
    metric_set->b_offset = metric_set->a_offset + 8;
    metric_set->c_offset = metric_set->b_offset + 8;
    metric_set->perfcnt_offset = metric_set->c_offset + 8;
    mtlgt3_test_oam_add_registers(perf, metric_set);
    intel_perf_add_metric_set(perf, metric_set);

    {
        static const struct intel_perf_logical_counter _counters[] = {

            {
                .name = "AVG GPU Core Frequency",
                .symbol_name = "AvgGpuCoreFrequency",
                .desc = "Average GPU Core Frequency in the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_HZ,
                .read_uint64 = mtlgt3__test_oam__avg_gpu_core_frequency__read,
                .max_uint64 = mtlgt3__test_oam__avg_gpu_core_frequency__max,
                .group = "GPU",
            },

            {
                .name = "TestCounter0",
                .symbol_name = "Counter0",
                .desc = "HW test counter 0. Factor: 0.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter0__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter1",
                .symbol_name = "Counter1",
                .desc = "HW test counter 1. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter1__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter2",
                .symbol_name = "Counter2",
                .desc = "HW test counter 2. Factor: 1.0",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter2__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter3",
                .symbol_name = "Counter3",
                .desc = "HW test counter 3. Factor: 0.5",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter3__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter4",
                .symbol_name = "Counter4",
                .desc = "HW test counter 4. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter4__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter5",
                .symbol_name = "Counter5",
                .desc = "HW test counter 5. Factor: 0.3333",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter5__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter6",
                .symbol_name = "Counter6",
                .desc = "HW test counter 6. Factor: 0.16666",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter6__read,
                .max_uint64 = NULL /* undefined */,
                .group = "Test",
            },

            {
                .name = "TestCounter8",
                .symbol_name = "Counter8",
                .desc = "TestCounter8",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_EVENTS,
                .read_uint64 = mtlgt3__test_oam__counter8__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Core Clocks",
                .symbol_name = "GpuCoreClocks",
                .desc = "The total number of GPU core clocks elapsed during the measurement.",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_CYCLES,
                .read_uint64 = mtlgt3__test_oam__gpu_core_clocks__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "GPU Time Elapsed",
                .symbol_name = "GpuTime",
                .desc = "GPU Time Elapsed",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_NS,
                .read_uint64 = mtlgt3__test_oam__gpu_time__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX0_READ_REQUEST_MPEC",
                .symbol_name = "VIDEO_DECODE_BOX0_READ_REQUEST_MPEC",
                .desc = "Number of VDBOX0 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__test_oam__video_decode_box0_read_request_mpec__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX0_READ_REQUEST_VISA",
                .symbol_name = "VIDEO_DECODE_BOX0_READ_REQUEST_VISA",
                .desc = "Number of VDBOX0 read requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__test_oam__video_decode_box0_read_request_visa__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX0_WRITE_REQUEST_MPEC",
                .symbol_name = "VIDEO_DECODE_BOX0_WRITE_REQUEST_MPEC",
                .desc = "Number of VDBOX0 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__test_oam__video_decode_box0_write_request_mpec__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },

            {
                .name = "VIDEO_DECODE_BOX0_WRITE_REQUEST_VISA",
                .symbol_name = "VIDEO_DECODE_BOX0_WRITE_REQUEST_VISA",
                .desc = "Number of VDBOX0 write requests",
                .type = INTEL_PERF_LOGICAL_COUNTER_TYPE_EVENT,
                .storage = INTEL_PERF_LOGICAL_COUNTER_STORAGE_UINT64,
                .unit = INTEL_PERF_LOGICAL_COUNTER_UNIT_MESSAGES,
                .read_uint64 = mtlgt3__test_oam__video_decode_box0_write_request_visa__read,
                .max_uint64 = NULL /* undefined */,
                .group = "GPU",
            },
        };
        int i;
        for (i = 0; i < sizeof(_counters) / sizeof(_counters[0]); i++) {
            if (_counters[i].availability && !_counters[i].availability(perf))
                continue;
            counter = &metric_set->counters[metric_set->n_counters++];
            *counter = _counters[i];
            counter->metric_set = metric_set;
            intel_perf_add_logical_counter(perf, counter, counter->group);
        }
    }

    assert(metric_set->n_counters <= 15);
}

void
intel_perf_load_metrics_mtlgt3(struct intel_perf *perf)
{
    mtlgt3_add_render_basic_metric_set(perf);
    mtlgt3_add_compute_basic_metric_set(perf);
    mtlgt3_add_async_compute_metric_set(perf);
    mtlgt3_add_xve_activity_metric_set(perf);
    mtlgt3_add_gpu_busyness_metric_set(perf);
    mtlgt3_add_hdc_and_sf1_metric_set(perf);
    mtlgt3_add_hdc_and_sf2_metric_set(perf);
    mtlgt3_add_l3_metric_set(perf);
    mtlgt3_add_rasterizer_and_pixel_backend1_metric_set(perf);
    mtlgt3_add_rasterizer_and_pixel_backend2_metric_set(perf);
    mtlgt3_add_render_pipe_profile1_metric_set(perf);
    mtlgt3_add_render_pipe_profile2_metric_set(perf);
    mtlgt3_add_sampler_metric_set(perf);
    mtlgt3_add_tdl1_metric_set(perf);
    mtlgt3_add_tdl2_metric_set(perf);
    mtlgt3_add_tdl3_metric_set(perf);
    mtlgt3_add_tdl4_metric_set(perf);
    mtlgt3_add_test_oa_metric_set(perf);
    mtlgt3_add_ext1_metric_set(perf);
    mtlgt3_add_ext3_metric_set(perf);
    mtlgt3_add_ext4_metric_set(perf);
    mtlgt3_add_ext5_metric_set(perf);
    mtlgt3_add_ext6_metric_set(perf);
    mtlgt3_add_ext7_metric_set(perf);
    mtlgt3_add_ext8_metric_set(perf);
    mtlgt3_add_ext9_metric_set(perf);
    mtlgt3_add_ext10_metric_set(perf);
    mtlgt3_add_ext11_metric_set(perf);
    mtlgt3_add_ext12_metric_set(perf);
    mtlgt3_add_ext13_metric_set(perf);
    mtlgt3_add_ext14_metric_set(perf);
    mtlgt3_add_ext15_metric_set(perf);
    mtlgt3_add_ext16_metric_set(perf);
    mtlgt3_add_ext17_metric_set(perf);
    mtlgt3_add_ext18_metric_set(perf);
    mtlgt3_add_ext21_metric_set(perf);
    mtlgt3_add_ext22_metric_set(perf);
    mtlgt3_add_ext23_metric_set(perf);
    mtlgt3_add_ext24_metric_set(perf);
    mtlgt3_add_ext28_metric_set(perf);
    mtlgt3_add_ext29_metric_set(perf);
    mtlgt3_add_ext31_metric_set(perf);
    mtlgt3_add_ext32_metric_set(perf);
    mtlgt3_add_ext35_metric_set(perf);
    mtlgt3_add_ext36_metric_set(perf);
    mtlgt3_add_ext39_metric_set(perf);
    mtlgt3_add_ext40_metric_set(perf);
    mtlgt3_add_ext43_metric_set(perf);
    mtlgt3_add_ext44_metric_set(perf);
    mtlgt3_add_ext45_metric_set(perf);
    mtlgt3_add_ext46_metric_set(perf);
    mtlgt3_add_ext51_metric_set(perf);
    mtlgt3_add_ext53_metric_set(perf);
    mtlgt3_add_ext54_metric_set(perf);
    mtlgt3_add_ext57_metric_set(perf);
    mtlgt3_add_ext58_metric_set(perf);
    mtlgt3_add_ext61_metric_set(perf);
    mtlgt3_add_ext62_metric_set(perf);
    mtlgt3_add_ext65_metric_set(perf);
    mtlgt3_add_ext66_metric_set(perf);
    mtlgt3_add_ext67_metric_set(perf);
    mtlgt3_add_ext68_metric_set(perf);
    mtlgt3_add_ext73_metric_set(perf);
    mtlgt3_add_ext74_metric_set(perf);
    mtlgt3_add_ext75_metric_set(perf);
    mtlgt3_add_ext76_metric_set(perf);
    mtlgt3_add_ext77_metric_set(perf);
    mtlgt3_add_ext78_metric_set(perf);
    mtlgt3_add_ext79_metric_set(perf);
    mtlgt3_add_ext80_metric_set(perf);
    mtlgt3_add_ext81_metric_set(perf);
    mtlgt3_add_ext82_metric_set(perf);
    mtlgt3_add_ext83_metric_set(perf);
    mtlgt3_add_ext85_metric_set(perf);
    mtlgt3_add_ext86_metric_set(perf);
    mtlgt3_add_ext87_metric_set(perf);
    mtlgt3_add_ext88_metric_set(perf);
    mtlgt3_add_ext91_metric_set(perf);
    mtlgt3_add_ext92_metric_set(perf);
    mtlgt3_add_ext93_metric_set(perf);
    mtlgt3_add_ext94_metric_set(perf);
    mtlgt3_add_ext95_metric_set(perf);
    mtlgt3_add_ext96_metric_set(perf);
    mtlgt3_add_ext97_metric_set(perf);
    mtlgt3_add_ext98_metric_set(perf);
    mtlgt3_add_ext99_metric_set(perf);
    mtlgt3_add_ext100_metric_set(perf);
    mtlgt3_add_ext101_metric_set(perf);
    mtlgt3_add_ext102_metric_set(perf);
    mtlgt3_add_ext103_metric_set(perf);
    mtlgt3_add_ext104_metric_set(perf);
    mtlgt3_add_ext105_metric_set(perf);
    mtlgt3_add_ext106_metric_set(perf);
    mtlgt3_add_ext107_metric_set(perf);
    mtlgt3_add_ext108_metric_set(perf);
    mtlgt3_add_ext109_metric_set(perf);
    mtlgt3_add_ext110_metric_set(perf);
    mtlgt3_add_ext111_metric_set(perf);
    mtlgt3_add_ext113_metric_set(perf);
    mtlgt3_add_ext114_metric_set(perf);
    mtlgt3_add_ext116_metric_set(perf);
    mtlgt3_add_ext117_metric_set(perf);
    mtlgt3_add_ext118_metric_set(perf);
    mtlgt3_add_ext119_metric_set(perf);
    mtlgt3_add_ext120_metric_set(perf);
    mtlgt3_add_ext121_metric_set(perf);
    mtlgt3_add_ext122_metric_set(perf);
    mtlgt3_add_ext123_metric_set(perf);
    mtlgt3_add_ext124_metric_set(perf);
    mtlgt3_add_ext125_metric_set(perf);
    mtlgt3_add_ext126_metric_set(perf);
    mtlgt3_add_ext127_metric_set(perf);
    mtlgt3_add_ext128_metric_set(perf);
    mtlgt3_add_ext129_metric_set(perf);
    mtlgt3_add_ext130_metric_set(perf);
    mtlgt3_add_ext131_metric_set(perf);
    mtlgt3_add_ext132_metric_set(perf);
    mtlgt3_add_ext133_metric_set(perf);
    mtlgt3_add_ext134_metric_set(perf);
    mtlgt3_add_ext135_metric_set(perf);
    mtlgt3_add_ext136_metric_set(perf);
    mtlgt3_add_ext137_metric_set(perf);
    mtlgt3_add_ext138_metric_set(perf);
    mtlgt3_add_ext139_metric_set(perf);
    mtlgt3_add_ext140_metric_set(perf);
    mtlgt3_add_ext141_metric_set(perf);
    mtlgt3_add_ext142_metric_set(perf);
    mtlgt3_add_ext143_metric_set(perf);
    mtlgt3_add_ext144_metric_set(perf);
    mtlgt3_add_ext145_metric_set(perf);
    mtlgt3_add_ext146_metric_set(perf);
    mtlgt3_add_ext147_metric_set(perf);
    mtlgt3_add_ext148_metric_set(perf);
    mtlgt3_add_ext149_metric_set(perf);
    mtlgt3_add_ext150_metric_set(perf);
    mtlgt3_add_ext151_metric_set(perf);
    mtlgt3_add_ext152_metric_set(perf);
    mtlgt3_add_ext153_metric_set(perf);
    mtlgt3_add_ext154_metric_set(perf);
    mtlgt3_add_ext155_metric_set(perf);
    mtlgt3_add_ext156_metric_set(perf);
    mtlgt3_add_ext158_metric_set(perf);
    mtlgt3_add_ext159_metric_set(perf);
    mtlgt3_add_ext160_metric_set(perf);
    mtlgt3_add_ext161_metric_set(perf);
    mtlgt3_add_ext162_metric_set(perf);
    mtlgt3_add_ext163_metric_set(perf);
    mtlgt3_add_ext164_metric_set(perf);
    mtlgt3_add_ext165_metric_set(perf);
    mtlgt3_add_ext166_metric_set(perf);
    mtlgt3_add_ext167_metric_set(perf);
    mtlgt3_add_ext168_metric_set(perf);
    mtlgt3_add_ext169_metric_set(perf);
    mtlgt3_add_ext170_metric_set(perf);
    mtlgt3_add_ext171_metric_set(perf);
    mtlgt3_add_ext172_metric_set(perf);
    mtlgt3_add_ext173_metric_set(perf);
    mtlgt3_add_ext174_metric_set(perf);
    mtlgt3_add_ext175_metric_set(perf);
    mtlgt3_add_ext176_metric_set(perf);
    mtlgt3_add_ext177_metric_set(perf);
    mtlgt3_add_ext178_metric_set(perf);
    mtlgt3_add_ext179_metric_set(perf);
    mtlgt3_add_ext180_metric_set(perf);
    mtlgt3_add_ext181_metric_set(perf);
    mtlgt3_add_ext182_metric_set(perf);
    mtlgt3_add_ext183_metric_set(perf);
    mtlgt3_add_ext184_metric_set(perf);
    mtlgt3_add_ext185_metric_set(perf);
    mtlgt3_add_ext186_metric_set(perf);
    mtlgt3_add_ext188_metric_set(perf);
    mtlgt3_add_ext189_metric_set(perf);
    mtlgt3_add_ext190_metric_set(perf);
    mtlgt3_add_ext191_metric_set(perf);
    mtlgt3_add_ext192_metric_set(perf);
    mtlgt3_add_ext193_metric_set(perf);
    mtlgt3_add_ext195_metric_set(perf);
    mtlgt3_add_ext196_metric_set(perf);
    mtlgt3_add_ext198_metric_set(perf);
    mtlgt3_add_ext199_metric_set(perf);
    mtlgt3_add_ext200_metric_set(perf);
    mtlgt3_add_ext201_metric_set(perf);
    mtlgt3_add_ext202_metric_set(perf);
    mtlgt3_add_ext203_metric_set(perf);
    mtlgt3_add_ext204_metric_set(perf);
    mtlgt3_add_ext205_metric_set(perf);
    mtlgt3_add_ext206_metric_set(perf);
    mtlgt3_add_ext207_metric_set(perf);
    mtlgt3_add_ext212_metric_set(perf);
    mtlgt3_add_ext213_metric_set(perf);
    mtlgt3_add_ext214_metric_set(perf);
    mtlgt3_add_ext215_metric_set(perf);
    mtlgt3_add_ext220_metric_set(perf);
    mtlgt3_add_ext225_metric_set(perf);
    mtlgt3_add_ext226_metric_set(perf);
    mtlgt3_add_ext227_metric_set(perf);
    mtlgt3_add_ext228_metric_set(perf);
    mtlgt3_add_ext229_metric_set(perf);
    mtlgt3_add_ext230_metric_set(perf);
    mtlgt3_add_ext231_metric_set(perf);
    mtlgt3_add_ext232_metric_set(perf);
    mtlgt3_add_ext236_metric_set(perf);
    mtlgt3_add_ext237_metric_set(perf);
    mtlgt3_add_ext239_metric_set(perf);
    mtlgt3_add_ext240_metric_set(perf);
    mtlgt3_add_ext500_metric_set(perf);
    mtlgt3_add_ext501_metric_set(perf);
    mtlgt3_add_ext502_metric_set(perf);
    mtlgt3_add_ext503_metric_set(perf);
    mtlgt3_add_ext508_metric_set(perf);
    mtlgt3_add_ext509_metric_set(perf);
    mtlgt3_add_ext510_metric_set(perf);
    mtlgt3_add_ext511_metric_set(perf);
    mtlgt3_add_ext512_metric_set(perf);
    mtlgt3_add_ext513_metric_set(perf);
    mtlgt3_add_ext514_metric_set(perf);
    mtlgt3_add_ext515_metric_set(perf);
    mtlgt3_add_ext516_metric_set(perf);
    mtlgt3_add_ext517_metric_set(perf);
    mtlgt3_add_ext518_metric_set(perf);
    mtlgt3_add_ext519_metric_set(perf);
    mtlgt3_add_ext520_metric_set(perf);
    mtlgt3_add_ext521_metric_set(perf);
    mtlgt3_add_ext522_metric_set(perf);
    mtlgt3_add_ext523_metric_set(perf);
    mtlgt3_add_ext524_metric_set(perf);
    mtlgt3_add_ext525_metric_set(perf);
    mtlgt3_add_ext526_metric_set(perf);
    mtlgt3_add_ext527_metric_set(perf);
    mtlgt3_add_ext528_metric_set(perf);
    mtlgt3_add_ext529_metric_set(perf);
    mtlgt3_add_ext530_metric_set(perf);
    mtlgt3_add_ext531_metric_set(perf);
    mtlgt3_add_ext540_metric_set(perf);
    mtlgt3_add_ext541_metric_set(perf);
    mtlgt3_add_ext542_metric_set(perf);
    mtlgt3_add_ext543_metric_set(perf);
    mtlgt3_add_ext544_metric_set(perf);
    mtlgt3_add_ext545_metric_set(perf);
    mtlgt3_add_ext546_metric_set(perf);
    mtlgt3_add_ext547_metric_set(perf);
    mtlgt3_add_ext604_metric_set(perf);
    mtlgt3_add_ext1000_metric_set(perf);
    mtlgt3_add_ext1001_metric_set(perf);
    mtlgt3_add_ext1002_metric_set(perf);
    mtlgt3_add_ext1003_metric_set(perf);
    mtlgt3_add_ext1004_metric_set(perf);
    mtlgt3_add_ext1005_metric_set(perf);
    mtlgt3_add_ext1006_metric_set(perf);
    mtlgt3_add_ext1007_metric_set(perf);
    mtlgt3_add_ext1010_metric_set(perf);
    mtlgt3_add_media_set1_metric_set(perf);
    mtlgt3_add_media_set2_metric_set(perf);
    mtlgt3_add_test_oam_metric_set(perf);
}
